Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet

42023E–SAM–07/2013

In combined transfers, the PECEN bit should only be written to one in the last of the combined
transfers. Consider the following transfer: 

S, ADR+W, COMMAND_BYTE, ACK, SR, ADR+R, DATA_BYTE, ACK, PEC_BYTE, NACK, P

This transfer is generated by writing two commands to the command registers. The first com-
mand is a write with NBYTES=1 and PECEN=0, and the second is a read with NBYTES=2 and
PECEN=1.

Writing a one to the STOP bit in CR will place a STOP condition on the bus after the current
byte. No PEC byte will be sent in this case.

The TLOWS and TLOWM fields in SMBTR configure the SMBus timeout values. If a timeout
occurs, the master will transmit a STOP condition and leave the bus. The SR.TOUT bit is set. 

This chapter lists the different bus events, and how they affect bits in the TWIM registers. This is
intended to help writing drivers for the TWIM.

Bus Events

Master transmitter has sent 
a data byte

SR.THR is cleared.

Master receiver has 
received a data byte

SR.RHR is set.

Start+Sadr sent, no ack 
received from slave

SR.ANAK is set.

SR.CCOMP not set.

CMDR.VALID remains set.

STOP automatically transmitted on bus.

Data byte sent to slave, no 
ack received from slave

SR.DNAK is set.

SR.CCOMP not set.

CMDR.VALID remains set.

STOP automatically transmitted on bus.

Arbitration lost

SR.ARBLST is set.

SR.CCOMP not set.

CMDR.VALID remains set.

TWCK and TWD immediately released to a pulled-up state.

SMBus timeout received

SR.SMBTOUT is set.

SR.CCOMP not set.

CMDR.VALID remains set.

STOP automatically transmitted on bus.