Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet

42023E–SAM–07/2013

The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. It is rec-
ommended to disable the TWIS before disabling the clock, to avoid freezing the TWIS in an
undefined state.

The TWIS DMA handshake interface is connected to the Peripheral DMA Controller. Using the
TWIS DMA functionality requires the Peripheral DMA Controller to be programmed after setting
up the TWIS.

The TWIS interrupt request lines are connected to the NVIC. Using the TWIS interrupts requires
the NVIC to be programmed first.

When an external debugger forces the CPU into debug mode, the TWIS continues normal oper-
ation. If the TWIS is configured in a way that requires it to be periodically serviced by the CPU
through interrupts or similar, improper operation or data loss may result during debugging.

The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see 

).

Each transfer begins with a START condition and terminates with a STOP condition (see 

).

• A high-to-low transition on the TWD line while TWCK is high defines the START condition.

• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.

Figure 28-3.  START and STOP Conditions 

Figure 28-4. Transfer Format

TWD

TWCK

Start

Stop

TWD

TWCK

Start

Address

R/W

Ack

Data

Ack

Data

Ack

Stop