Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet
Product codes
ATSAM4L-EK
776
42023E–SAM–07/2013
ATSAM4L8/L4/L2
28.10 Module Configuration
The specific configuration for each TWIS instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks. Refer to
bus clocks listed here are connected to the system bus clocks. Refer to
for details.
Note : TWI2 and TWI3 are master only. TWI0 and TWI1 are master and slave
Table 28-7.
Module Clock Name
Module Name
Clock Name
Description
TWIS0
CLK_TWIS0
Clock for the TWIS0 bus interface
TWIS1
CLK_TWIS1
Clock for the TWIS1 bus interface
Table 28-8.
Register Reset Values
Register
Reset Value
VERSION
0x00000140
PARAMETER
0x00000001