Atmel SAM4L-EK Atmel ATSAM4L-EK ATSAM4L-EK Data Sheet
Product codes
ATSAM4L-EK
97
42023E–SAM–07/2013
ATSAM4L8/L4/L2
8.11.8
Chip Erase Typical Procedure
The chip erase operation is triggered by writing a one in the CE bit in the Control Register
(CR.CE). This clears first all volatile memories in the system and second the whole flash array.
Note that the User page is not erased in this process. To ensure that the chip erase operation is
completed, check the DONE bit in the Status Register (SR.DONE). Also note that the chip erase
operation depends on clocks and power management features that can be altered by the CPU.
It is important to ensure that it is stopped. The recommended sequence is shown below:
(CR.CE). This clears first all volatile memories in the system and second the whole flash array.
Note that the User page is not erased in this process. To ensure that the chip erase operation is
completed, check the DONE bit in the Status Register (SR.DONE). Also note that the chip erase
operation depends on clocks and power management features that can be altered by the CPU.
It is important to ensure that it is stopped. The recommended sequence is shown below:
1.
At power up, RESET_N is driven low by a debugger. The on-chip regulator holds the
system in a POR state until the input supply is above the POR threshold. The system
continues to be held in this static state until the internally regulated supplies have
reached a safe operating.
system in a POR state until the input supply is above the POR threshold. The system
continues to be held in this static state until the internally regulated supplies have
reached a safe operating.
2.
PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash
Clock, and any Bus Clocks that do not have clock gate control). Internal resets are
maintained due to the external reset.
Clock, and any Bus Clocks that do not have clock gate control). Internal resets are
maintained due to the external reset.
– The debug port and access ports receives a clock and leave the reset state
3.
The debugger maintains a low level on TCK and release RESET_N.
– The SMAP asserts the core_hold_reset signal
4.
The Cortex-M4 core remains in reset state, meanwhile the rest of the system is
released.
released.
5.
The Chip erase operation can be performed by issuing the SMAP Chip Erase com-
mand. In this case:
mand. In this case:
– volatile memories are cleared first
– followed by the clearing of the flash array
– followed by the clearing of the protected state
6.
After operation is completed, the device must be restarted by either controling
RESET_N or switching power off/on. Make sure that the TCK pin is high when releas-
ing RESET_N not to halt the core.
RESET_N or switching power off/on. Make sure that the TCK pin is high when releas-
ing RESET_N not to halt the core.
8.11.9
Setting the Protected State
This is done by issuing a specific flash controller command, for more information, refer to
and to
. The protected state is defined by a highly secure
Flash builtin mechanism. Note that for this programmation to propagate, it is required to reset
the device.
the device.