Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet
Product codes
ATSAM4L-XSTK
366
42023E–SAM–07/2013
ATSAM4L8/L4/L2
RXINI should always be cleared before clearing FIFOCON to avoid missing an RXINI event.
Figure 17-17. Example of an IN pipe with one data bank
Figure 17-18. Example of an IN pipe with two data banks
• Multi packet mode for IN pipes
See
and just replace OUT endpoints with
IN pipe.
17.6.3.12
Management of OUT pipes
• Overview
OUT packets are sent by the host. All the data can be written, acknowledging whether or not the
bank is full.
bank is full.
• Detailed description
The pipe and its descriptor in RAM must be pre configured.
When the current bank is clear, the Transmitted OUT Data Interrupt (TXOUTI) and FIFO Control
(UPSTAn.FIFOCON) bits will be set simultaneously. This triggers a PnINT interrupt if the Trans-
mitted OUT Data Interrupt Enable bit (UPCONn.TXOUTE) is one.
(UPSTAn.FIFOCON) bits will be set simultaneously. This triggers a PnINT interrupt if the Trans-
mitted OUT Data Interrupt Enable bit (UPCONn.TXOUTE) is one.
IN
DATA
(bank 0)
ACK
RXINI
FIFOCON
HW
IN
DATA
(bank 0)
ACK
HW
SW
SW
SW
read data from CPU
BANK 0
read data from CPU
BANK 0
IN
DATA
(bank 0)
ACK
RXINI
FIFOCON
HW
IN
DATA
(bank 1)
ACK
SW
SW
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 1