Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet

42023E–SAM–07/2013

Figure 17-21. Example of an OUT pipe with two data banks and a bank switching delay

See section 

 and just replace IN endpoints with

OUT pipe.

The user has the possibility to run sequentially several logical pipes on the same physical pipe.

Before switching pipe, the user should save the pipe context (UPCFGn, UPCONn, UPSTAn,
and the pipe descriptor table).

After switching pipe, the user should restore the pipe context, current bank number, and the cur-
rent data toggle by using the UPCONn.INITDTGL and UPCONn.INITBK bits.

This error exists only for isochronous and interrupt pipes for both IN and OUT directions. It sets
the Errorflow Interrupt (ERRORFI) bit in UPSTAn, which triggers an PnINT interrupt if the Error-
f l o w   I n t e r r u p t   E n a b l e   ( E R R O R F E )   b i t   i s   o n e .   T h e   u s e r   c a n   c h e c k   t h e
Pn_CTR_STA_BK0/1.UNDERF and OVERF bits in the pipe descriptor to see which current
bank has been affected.

• An overflow can occur during an OUT stage if the host attempts to send data from an empty 

bank. The pipe descriptor Pn_CTR_STA_BK0/1.OVERF points out the bank from which the 
OUT data should have originated. If the UPSTAn.ERRORFI bit is cleared and a new 
transaction is successful, the Pn_CTR_STA_BK0/1.OVERF bit will be cleared.

• An underflow can occur during an IN stage if the device tries to send a packet while the bank 

is full. Typically this occurs when a CPU is not fast enough. The packet data is not written to 
the bank and is lost. The pipe descriptor Pn_CTR_STA_BK0/1.UNDERF points out which 
bank the OUT data was destined to. If UPSTAn.UNDERFI is zero and a new successful 
transaction occurs, Pn_CTR_STA_BK0/1.UNDERF will be cleared.

This error exists only for isochronous IN pipes. It sets the CRC Error Interrupt bit (CRCERRI),
which triggers a PnINT interrupt if the CRC Error Interrupt Enable bit (UPCONn.CRCERRE) is
one.

OUT

DATA

(bank 0)

ACK

TXOUTI

FIFOCON

write data to CPU

BANK 0

SW

SW

SW

SW

OUT

DATA

(bank 1)

ACK

write data to CPU

BANK 1

SW

HW

write data to CPU

BANK0