Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet
Product codes
ATSAM4L-XSTK
482
42023E–SAM–07/2013
ATSAM4L8/L4/L2
20.4.1
Power Management
When the WDT is enabled, it remains clocked in all sleep modes. It is not possible to enter sleep
modes where the source clock of CLK_CNT is stopped. Attempting to do so will result in the chip
entering the lowest sleep mode where the source clock is running, leaving the WDT operational.
Refer to
modes where the source clock of CLK_CNT is stopped. Attempting to do so will result in the chip
entering the lowest sleep mode where the source clock is running, leaving the WDT operational.
Refer to
for details about sleep modes.
After a watchdog reset the WDT bit in the Reset Cause Register (RCAUSE) in the Power Man-
ager will be set.
ager will be set.
20.4.2
Clocks
The clock for the WDT bus interface (CLK_WDT) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the WDT before disabling the clock, to avoid freezing the WDT in an undefined state.
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the WDT before disabling the clock, to avoid freezing the WDT in an undefined state.
There are two possible clock sources for the Watchdog Timer clock, CLK_CNT:
• System RC oscillator (RCSYS): This oscillator is always enabled when selected as clock
source for the WDT. Refer to
for details
about the RCSYS and sleep modes. Refer to
for the characteristic frequency of this oscillator.
• 32 kHz crystal oscillator or RC oscillator (OSC32 or RC32): This oscillator has to be enabled
in the Backup System Control Interface (BSCIF) before using it as clock source for the WDT.
Selection between OSC32 and RC32 should be done in the Backup Power Manager.The
WDT will not be able to detect if this clock is stopped.
Selection between OSC32 and RC32 should be done in the Backup Power Manager.The
WDT will not be able to detect if this clock is stopped.
20.4.3
Interrupt
The WDT interrupt request line is connected to the NVIC. Using the WDT interrupt requires the
NVIC to be programmed first.
NVIC to be programmed first.
20.4.4
Debug Operation
The WDT counter is not frozen during debug operation, unless the Core is halted and the bit cor-
responding to the WDT is set in the Peripheral Debug Register (PDBG). If the WDT counter is
not frozen during debug operation it will need periodically clearing to avoid a watchdog reset.
responding to the WDT is set in the Peripheral Debug Register (PDBG). If the WDT counter is
not frozen during debug operation it will need periodically clearing to avoid a watchdog reset.
20.4.5
Fuses
The WDT can be enabled at reset. This is controlled by the WDTAUTO fuse, see
for details. Refer to the Fuse Settings section in the Flash Controller chapter for details about
WDTAUTO and how to program the fuses.
WDTAUTO and how to program the fuses.
20.5
Functional Description
20.5.1
Basic Mode
20.5.1.1
WDT Control Register Access
To avoid accidental disabling of the watchdog, the Control Register (CTRL) must be written
twice, first with the KEY field set to 0x55, then 0xAA without changing the other bits. Failure to
do so will cause the write operation to be ignored, and the value in the CTRL Register will not be
changed.
twice, first with the KEY field set to 0x55, then 0xAA without changing the other bits. Failure to
do so will cause the write operation to be ignored, and the value in the CTRL Register will not be
changed.
20.5.1.2
Changing CLK_CNT Clock Source
After any reset, except for watchdog reset, CLK_CNT will be enabled with RCSYS as source.