Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet
Product codes
ATSAM4L-XSTK
544
42023E–SAM–07/2013
ATSAM4L8/L4/L2
Figure 23-3. Output Pin Timings
23.6.2.4
Pin Output Driver Control
The GPIO has registers for controlling output drive properties of each pin, such as output driving
capability and slew rate control.
capability and slew rate control.
The driving capability is controlled by the Output Driving Capability Registers (ODCRn) and the
slew rate settings are controlled by the Output Slew Rate Registers (OSRRn).
slew rate settings are controlled by the Output Slew Rate Registers (OSRRn).
For a GPIO pin with four different slew rate settings, a slew rate of two can be selected by writing
a zero to the OSRR0 register at the bit position corresponding to the GPIO pin, and a one to the
OSRR1 at the same bit position. The ODCRn registers are configured in the same way.
a zero to the OSRR0 register at the bit position corresponding to the GPIO pin, and a one to the
OSRR1 at the same bit position. The ODCRn registers are configured in the same way.
23.6.2.5
Input Schmitt Trigger
Each GPIO pin can be configured with an input Schmitt trigger. An input Schmitt trigger filters
input signal using an hysteresis function, stopping noise from propagation into the system. The
input Schmitt trigger can be enabled and disabled by writing a one and a zero respectively to the
Schmitt Trigger Enable Register (STER).
input signal using an hysteresis function, stopping noise from propagation into the system. The
input Schmitt trigger can be enabled and disabled by writing a one and a zero respectively to the
Schmitt Trigger Enable Register (STER).
23.6.2.6
Interrupts
The GPIO can be configured to generate an interrupt when it detects a change on a GPIO pin.
Interrupts on a pin are enabled by writing a one to the corresponding bit in the Interrupt Enable
Register (IER). The module can be configured to generate an interrupt whenever a pin changes
value, or only on rising or falling edges. This is controlled by the Interrupt Mode Registers
(IMRn). Interrupts on a pin can be enabled regardless of the GPIO pin being controlled by the
GPIO or assigned to a peripheral function.
Interrupts on a pin are enabled by writing a one to the corresponding bit in the Interrupt Enable
Register (IER). The module can be configured to generate an interrupt whenever a pin changes
value, or only on rising or falling edges. This is controlled by the Interrupt Mode Registers
(IMRn). Interrupts on a pin can be enabled regardless of the GPIO pin being controlled by the
GPIO or assigned to a peripheral function.
An interrupt can be generated on each GPIO pin. These interrupt generators are further grouped
into groups of eight and connected to the NVIC. An interrupt request from any of the GPIO pin
generators in the group will result in an interrupt request from that group to the NVIC if the corre-
sponding bit for the GPIO pin in the IER is set. By grouping interrupt generators into groups of
eight, four different interrupt handlers can be installed for each GPIO port.
into groups of eight and connected to the NVIC. An interrupt request from any of the GPIO pin
generators in the group will result in an interrupt request from that group to the NVIC if the corre-
sponding bit for the GPIO pin in the IER is set. By grouping interrupt generators into groups of
eight, four different interrupt handlers can be installed for each GPIO port.
The Interrupt Flag Register (IFR) can be read by software to determine which pin(s) caused the
interrupt. The interrupt flag must be manually cleared by writing a zero to the corresponding bit
in IFR.
interrupt. The interrupt flag must be manually cleared by writing a zero to the corresponding bit
in IFR.
GPIO interrupts will only be generated when CLK_GPIO is enabled.
23.6.2.7
Input Glitch Filter
Input glitch filters can be enabled on each GPIO pin. When the glitch filter is enabled, a glitch
with duration of less than 1 CLK_GPIO cycle is automatically rejected, while a pulse with dura-
with duration of less than 1 CLK_GPIO cycle is automatically rejected, while a pulse with dura-
PB Access
PB Access
CLK_GPIO
Write OVR to 1
Write OVR to 0
OVR / I/O Line
PVR