Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet
Product codes
ATSAM4L-XSTK
545
42023E–SAM–07/2013
ATSAM4L8/L4/L2
tion of 2 CLK_GPIO cycles or more is accepted. For pulse durations between 1 and 2
CLK_GPIO cycles, the pulse may or may not be taken into account, depending on the precise
timing of its occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 CLK_GPIO
cycles, whereas for a glitch to be reliably filtered out, its duration must not exceed 1 CLK_GPIO
cycle. The filter introduces 2 clock cycles latency.
CLK_GPIO cycles, the pulse may or may not be taken into account, depending on the precise
timing of its occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 CLK_GPIO
cycles, whereas for a glitch to be reliably filtered out, its duration must not exceed 1 CLK_GPIO
cycle. The filter introduces 2 clock cycles latency.
The glitch filters are controlled by the Glitch Filter Enable Register (GFER). When a bit in GFER
is one, the glitch filter on the corresponding pin is enabled. The glitch filter affects only interrupt
inputs. Inputs to peripherals or the value read through PVR are not affected by the glitch filters.
is one, the glitch filter on the corresponding pin is enabled. The glitch filter affects only interrupt
inputs. Inputs to peripherals or the value read through PVR are not affected by the glitch filters.
23.6.2.8
Interrupt Timings
shows the timing for rising edge (or pin-change) interrupts when the glitch filter is
disabled. For the pulse to be registered, it must be sampled at the rising edge of the clock. In this
example, this is not the case for the first pulse. The second pulse is sampled on a rising edge
and will trigger an interrupt request.
example, this is not the case for the first pulse. The second pulse is sampled on a rising edge
and will trigger an interrupt request.
Figure 23-4. Interrupt Timing with Glitch Filter Disabled
shows the timing for rising edge (or pin-change) interrupts when the glitch filter is
enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges. In
the example, the first pulse is rejected while the second pulse is accepted and causes an inter-
rupt request.
the example, the first pulse is rejected while the second pulse is accepted and causes an inter-
rupt request.
Figure 23-5. Interrupt Timing with Glitch Filter Enabled
23.6.2.9
Peripheral Events
Peripheral events allow direct peripheral to peripheral communication of specified events. See
for more information.
The GPIO can be programmed to output peripheral events whenever an interrupt condition is
detected. The peripheral events configuration depends on the interrupt configuration. An event
will be generated on the same condition as the interrupt (pin change, rising edge, or falling
edge). The interrupt configuration is controlled by the IMR register. Peripheral event on a pin is
enabled by writing a one to the corresponding bit in the Event Enable Register (EVER). The
Peripheral Event trigger mode is shared with the interrupt trigger and is configured by writing to
the IMR0 and IMR1 registers. Interrupt does not need to be enabled on a pin when peripheral
detected. The peripheral events configuration depends on the interrupt configuration. An event
will be generated on the same condition as the interrupt (pin change, rising edge, or falling
edge). The interrupt configuration is controlled by the IMR register. Peripheral event on a pin is
enabled by writing a one to the corresponding bit in the Event Enable Register (EVER). The
Peripheral Event trigger mode is shared with the interrupt trigger and is configured by writing to
the IMR0 and IMR1 registers. Interrupt does not need to be enabled on a pin when peripheral
CLK_GPIO
Pin Level
IFR
CLK_GPIO
Pin Level
IFR