Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

Product codes
ATSAMD21-XPRO
Page of 1018
113
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
Figure 15-3. Reset Controller
15.6.2.8  Sleep Mode Controller
Sleep mode is activated by the Wait For Interrupt instruction (WFI). The Idle bits in the Sleep Mode register 
(SLEEP.IDLE) and the SLEEPDEEP bit of the System Control register of the CPU should be used as argument to select 
the level of the sleep mode.
There are two main types of sleep mode:
z
IDLE mode: The CPU is stopped. Optionally, some synchronous clock domains are stopped, depending on the 
IDLE argument. Regulator operates in normal mode.
z
STANDBY mode: All clock sources are stopped, except those where the RUNSTDBY bit is set. Regulator operates 
in low-power mode. Before entering standby mode the user must make sure that a significant amount of clocks 
and peripherals are disabled, so that the voltage regulator is not overloaded.
Notes:
1.
Asynchronous: interrupt generated on generic clock or external clock or external event.
2.
Synchronous: interrupt generated on the APB clock.
RESET CONTROLLER
BOD12
BOD33
POR
WDT
RESET
RESET SOURCES
RTC
32kHz clock sources
WDT with ALWAYSON
Generic Clock with 
WRTLOCK
Debug Logic
Others
CPU
RCAUSE
Table 15-3. Sleep Mode Entry and Exit Table
Mode
Level
Mode Entry
Wake-Up Sources
IDLE
0
SCR.SLEEPDEEP = 0
SLEEP.IDLE=Level
WFI
Synchronous
 (APB, AHB), asynchronous
1
Synchronous (APB), asynchronous
2
Asynchronous
STANDBY
SCR.SLEEPDEEP = 1
WFI
Asynchronous