Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
147
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
16.6.7.2 Additional Features
Dealing with Delay in the DFLL in Closed-Loop Mode
The time from selecting a new CLK_DFLL48M frequency until this frequency is output by the DFLL48M can be up to
several microseconds. If the value in DFLLMUL.MUL is small, this can lead to instability in the DFLL48M locking
mechanism, which can prevent the DFLL48M from achieving locks. To avoid this, a chill cycle, during which the
CLK_DFLL48M frequency is not measured, can be enabled. The chill cycle is enabled by default, but can be disabled by
writing a one to the DFLL Chill Cycle Disable bit (DFLLCTRL.CCDIS) in the DFLL Control register. Enabling chill cycles
might double the lock time.
several microseconds. If the value in DFLLMUL.MUL is small, this can lead to instability in the DFLL48M locking
mechanism, which can prevent the DFLL48M from achieving locks. To avoid this, a chill cycle, during which the
CLK_DFLL48M frequency is not measured, can be enabled. The chill cycle is enabled by default, but can be disabled by
writing a one to the DFLL Chill Cycle Disable bit (DFLLCTRL.CCDIS) in the DFLL Control register. Enabling chill cycles
might double the lock time.
Another solution to this problem consists of using less strict lock requirements. This is called Quick Lock (QL), which is
also enabled by default, but it can be disabled by writing a one to the Quick Lock Disable bit (DFLLCTRL.QLDIS) in the
DFLL Control register. The Quick Lock might lead to a larger spread in the output frequency than chill cycles, but the
average output frequency is the same.
also enabled by default, but it can be disabled by writing a one to the Quick Lock Disable bit (DFLLCTRL.QLDIS) in the
DFLL Control register. The Quick Lock might lead to a larger spread in the output frequency than chill cycles, but the
average output frequency is the same.
USB Clock Recovery Mode
USB Clock Recovery mode can be used to create the 48MHz USB clock from the USB Start Of Frame (SOF). The mode
is enabled by writing a one to the USB Clock Recovery Mode bit in DFLL Control register (DFLLCTRL.USBCRM).
is enabled by writing a one to the USB Clock Recovery Mode bit in DFLL Control register (DFLLCTRL.USBCRM).
The SOF signal from USB device will be used as reference clock (CLK_DFLL_REF), ignoring the selected generic clock
reference. When the USB device is connected, a SOF will be sent every 1ms, thus DFLLVAL.MUX bits should be written
to 0xBB80 to obtain a 48MHz clock. In USB clock recovery mode, the DFLLCTRL.BPLCKC bit state is ignored and the
value stored in the DFLLVAL.COARSE will be used as COARSE final value. The lock procedure will also go
instantaneously to the fine lock search. The COARSE calibration value can be loaded from NVM OTP row by software.
DFLLCTRL.QLDIS bit must be cleared and DFLLCTRL.CCDIS should be set to speed up the lock phase. The
DFLLCTRL.STABLE bit state is ignored to let an auto jitter reduction mechanism working instead.
reference. When the USB device is connected, a SOF will be sent every 1ms, thus DFLLVAL.MUX bits should be written
to 0xBB80 to obtain a 48MHz clock. In USB clock recovery mode, the DFLLCTRL.BPLCKC bit state is ignored and the
value stored in the DFLLVAL.COARSE will be used as COARSE final value. The lock procedure will also go
instantaneously to the fine lock search. The COARSE calibration value can be loaded from NVM OTP row by software.
DFLLCTRL.QLDIS bit must be cleared and DFLLCTRL.CCDIS should be set to speed up the lock phase. The
DFLLCTRL.STABLE bit state is ignored to let an auto jitter reduction mechanism working instead.
Wake from Sleep Modes
DFLL48M can optionally reset its lock bits when it is disabled. This is configured by the Lose Lock After Wake bit
(DFLLCTRL.LLAW) in the DFLL Control register. If DFLLCTRL.LLAW is zero, the DFLL48M will be re-enabled and start
running with the same configuration as before being disabled, even if the reference clock is not available. The locks will
not be lost. When the reference clock has restarted, the Fine tracking will quickly compensate for any frequency drift
during sleep if DFLLCTRL.STABLE is zero. If DFLLCTRL.LLAW is one when the DFLL is turned off, the DFLL48M will
lose all its locks, and needs to regain these through the full lock sequence.
(DFLLCTRL.LLAW) in the DFLL Control register. If DFLLCTRL.LLAW is zero, the DFLL48M will be re-enabled and start
running with the same configuration as before being disabled, even if the reference clock is not available. The locks will
not be lost. When the reference clock has restarted, the Fine tracking will quickly compensate for any frequency drift
during sleep if DFLLCTRL.STABLE is zero. If DFLLCTRL.LLAW is one when the DFLL is turned off, the DFLL48M will
lose all its locks, and needs to regain these through the full lock sequence.
Accuracy
There are three main factors that determine the accuracy of F
clkdfll48m
. These can be tuned to obtain maximum accuracy
when fine lock is achieved.
z
Fine resolution: The frequency step between two Fine values. This is relatively smaller for high output frequencies.
z
Resolution of the measurement: If the resolution of the measured F
clkdfll48m
is low, i.e., the ratio between the
CLK_DFLL48M frequency and the CLK_DFLL48M_REF frequency is small, then the DFLL48M might lock at a
frequency that is lower than the targeted frequency. It is recommended to use a reference clock frequency of
32kHz or lower to avoid this issue for low target frequencies.
frequency that is lower than the targeted frequency. It is recommended to use a reference clock frequency of
32kHz or lower to avoid this issue for low target frequencies.
z
The accuracy of the reference clock.
16.6.8 FDPLL96M – Fractional Digital Phase-Locked Loop Controller
16.6.8.1 Overview
The FDPLL96M controller allows flexible interface to the core digital function of the Digital Phase Locked Loop (DPLL).
The FDPLL96M integrates a digital filter with a proportional integral controller, a Time-to-Digital Converter (TDC), a test
mode controller, a Digitally Controlled Oscillator (DCO) and a PLL controller. It also provides a fractional multiplier of
frequency N between the input and output frequency.
The FDPLL96M integrates a digital filter with a proportional integral controller, a Time-to-Digital Converter (TDC), a test
mode controller, a Digitally Controlled Oscillator (DCO) and a PLL controller. It also provides a fractional multiplier of
frequency N between the input and output frequency.
The CLK_FDPLL96M_REF is the DPLL input clock reference. The selectable sources for the reference clock are
XOSC32K, XOSC and GCLK_DPLL. The path between XOSC and input multiplexer integrates a clock divider.
XOSC32K, XOSC and GCLK_DPLL. The path between XOSC and input multiplexer integrates a clock divider.