Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

148

Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

The selected clock must be configured and enabled before using the FDPLL96M. If the GCLK is selected as reference 
clock, it must be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to 

“GCLK – 

Generic Clock Controller” on page 84

 for details.If the GCLK_DPLL is selected as the source for the 

CLK_FDPLL96M_REF, care must be taken to make sure the source for this GCLK is within the valid frequency range for 
the FDPLL96M.

The XOSC source can be divided inside the FDPLL96M. The user must make sure that the programmable clock divider 
and XOSC frequency provides a valid CLK_FDPLL96M_REF clock frequency that meets the FDPLL96M input frequency 
range.

The output clock of the FDPLL96M is CLK_FDPLL96M. The state of the CLK_FDPLL96M clock only depends on the 
FDPLL96M internal control of the final clock gater CG. 

The FDPLL96M requires a 32kHz clock from the GCLK when the FDPLL96M internal lock timer is used. This clock must 
be configured and enabled in the Generic Clock Controller before using the FDPLL96M. Refer to 

“GCLK – Generic Clock 

Controller” on page 84

 for details.

The task of the FDPLL96M is to maintain coherence between the input reference clock signal (CLK_FDPLL96M_REF) 
and the respective output frequency CK via phase comparison. The FDPLL96M supports three independent sources of 
clocks XOSC32K, XOSC and GCLK_DPLL. When the FDPLL96M is enabled, the relationship between the reference 
clock (CLK_FDPLL96M_REF) frequency and the output clock (CLK_FDPLL96M) frequency is defined below.

Where LDR is the loop divider ratio integer part, LDRFRAC is the loop divider ratio fractional part, f

ckrx

 is the frequency of 

the selected reference clock and f

ck

 is the frequency of the FDPLL96M output clock. As previously stated a clock divider 

exist between XOSC and CLK_FDPLL96M_REF. The frequency between the two clocks is defined below.

FDPLL96M 32kHz clock

GCLK_DPLL_32K for internal lock timer

FDPLL96M

GCLK_DPLL for CLK_FDPLL96M_REF

TDC

Digital
Filter

DCO

÷N

XOSC32K

XOSC

CK

%JWJEFS

GCLK_DPLL

$(

CLK_FDPLL96M

User
Interface

CLK_FDPLL96M_REF

GCLK_DPLL_32K

clk_fdpll96m

clk_fdpll96m_ref

LDR 1

16

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