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Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

Product codes
ATSAMD21-XPRO
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Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
19.6.2 Basic Operation
19.6.2.1  Initialization
The following DMAC registers are enable-protected, meaning that they can only be written when the DMAC is disabled 
(
z
Descriptor Base Memory Address (
) register
z
Write-Back Memory Base Address (
) register
The following DMAC bit is enable-protected, meaning that it can only be written when both the DMAC and CRC are 
disabled (
.CRCENABLE is zero):
z
Software Reset bit in Control register (CTRL.SWRST)
The following DMA channel register is enable-protected, meaning that it can only be written when the corresponding 
DMA channel is disabled (
.ENABLE is zero):
z
.CMD) and Channel Arbitration Level 
.LVL) bits
The following DMA channel bit is enable-protected, meaning that it can only be written when the corresponding DMA 
channel is disabled:
z
Channel Software Reset bit in Channel Control A register (
.SWRST)
The following CRC registers are enable-protected, meaning that they can only be written when the CRC is disabled 
(
.CRCENABLE is zero):
z
) register
z
) register
Enable-protection is denoted by the Enable-Protected property in the register description.
Before the DMAC is enabled, it must be configured, as outlined by the following steps:
z
The SRAM address of where the descriptor memory section is located must be written to the Description Base 
Address (
z
The SRAM address of where the write-back section should be located must be written to the Write-Back Memory 
Base Address (
z
Priority level x of the arbiter can be enabled by writing a one to the Priority Level x Enable bit in the Control 
register(
.LVLENx)
Before a DMA channel is enabled, the DMA channel and the corresponding first transfer descriptor must be configured, 
as outlined by the following steps:
z
DMA channel configurations
z
The channel number of the DMA channel to configure must be written to the Channel ID (
) register
z
Trigger action must be selected by writing the Trigger Action bit group in the Channel Control B register  
(
.TRIGACT)
z
Trigger source must be selected by writing the Trigger Source bit group in the Channel Control B register 
(
.TRIGSRC)
z
Transfer Descriptor
z
The size of each access of the data transfer bus must be selected by writing the Beat Size bit group in the 
Block Transfer Control register (
.BEATSIZE)
z
The transfer descriptor must be made valid by writing a one to the Valid bit in the Block Transfer Control 
register (
.VALID)
z
Number of beats in the block transfer must be selected by writing the Block Transfer Count (
) 
register
z
Source address for the block transfer must be selected by writing the Block Transfer Source Address 
(
) register