Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
263
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
19.5.1 I/O Lines
Not applicable.
19.5.2 Power Management
The DMAC will continue to operate in any sleep mode where the selected source clock is running. The DMAC’s interrupts
can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations
in the system without exiting sleep modes. Refer to
can be used to wake up the device from sleep modes. Events connected to the event system can trigger other operations
in the system without exiting sleep modes. Refer to
modes. On hardware or software reset, all registers are set to their reset value.
19.5.3 Clocks
The DMAC bus clock (CLK_DMAC_APB) can be enabled and disabled in the power manager, and the default state of
CLK_DMAC_APB can be found in
CLK_DMAC_APB can be found in
An AHB clock (CLK_DMAC_AHB) is required to clock the DMAC. This clock must be configured and enabled in the
power manager before using the DMAC, and the default state of CLK_DMAC_AHB can be found in
power manager before using the DMAC, and the default state of CLK_DMAC_AHB can be found in
.
This bus clock (CLK_DMAC_APB) is always synchronous to the module clock (CLK_DMAC_AHB), but can be divided by
a prescaler and may run even when the module clock is turned off.
a prescaler and may run even when the module clock is turned off.
19.5.4 DMA
Not applicable.
19.5.5 Interrupts
The interrupt request line is connected to the interrupt controller. Using the DMAC interrupts requires the interrupt
controller to be configured first. Refer to
controller to be configured first. Refer to
for details.
19.5.6 Events
configure the Event System.
19.5.7 Debug Operation
When the CPU is halted in debug mode the DMAC will halt normal operation. The DMAC can be forced to continue
operation during debugging. Refer to
operation during debugging. Refer to
19.5.8 Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following registers:
following registers:
z
Interrupt Pending (
z
) register
z
Channel Interrupt Flag Status and Clear (
) register
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through an external debugger. Refer to
19.5.9 Analog Connections
Not applicable.