Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

268

Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

If a DMA channel is enabled and not suspended when it receives a transfer trigger, it will send a transfer request to the 
arbiter. When the arbiter receives the transfer request it will include the DMA channel in the queue of channels having 
pending transfers, and the corresponding Pending Channel x bit in the Pending Channels registers 
(

.PENDCHx) will be set. Dependent of the arbitration scheme, the arbiter will choose which DMA channel will 

be the next active channel. Refer to 

. The active channel is the DMA channel being granted access to perform 

its next burst transfer. When the arbiter has granted a DMA channel access to the DMAC, the corresponding 

.PENDCHx will be cleared. Depending on if the upcoming burst transfer is the first for the transfer request or 

not, the corresponding Busy Channel x bit in the Busy Channels register (

.BUSYCHx) will either be set or 

remain one. When the channel has performed its granted burst transfer(s) it will either be fed into the queue of channels 
with pending transfers, set to be waiting for a new transfer trigger, it will be suspended or it will be disabled. This depends 
on the channel and block transfer configuration. If the DMA channel is fed into the queue of channels with pending 
transfers, the corresponding 

.BUSYCHx will remain one. If the DMA channel is set to wait for a new transfer 

.BUSYCHx will be cleared.

If a DMA channel is suspended while it has a pending transfer, it will be removed from the queue of pending channels, 
but the corresponding 

.PENDCHx will remain set. When the same DMA channel is resumed, it will be added to 

the queue of pending channels again. If a DMA channel gets disabled(

.ENABLE is zero) while it has a pending 

transfer, it will be removed from the queue of pending channels, and the corresponding 

.PENDCHx will be 

cleared.

When a channel level is pending or the channel is transferring data, the corresponding Level Executing bit is set in the 
Active Channel and Levels register (

.LVLEXx).

Each DMA channel supports a 4-level priority scheme. The priority level for a channel is configured by writing to the 
Channel Arbitration Level bit group in the Channel Control B register(

.LVL). As long as all priority levels are 

enabled, a channel with lower priority level number will have priority over a channel with higher priority level number. A 
priority level is enabled by writing the Priority Level x Enable bit in the Control register(

.LVLENx) to one, for the 

corresponding level.

Within each priority level the DMAC's arbiter can be configured to prioritize statically or dynamically. For the arbiter to 
perform static arbitration within a priority level, the Level x Round-Robin Scheduling Enable bit in the Priority Control 0 
register (

.RRLVLENx) has to be written to zero. When static arbitration is enabled (

.RRLVLENx is 

zero), the arbiter will prioritize a low channel number over a high channel number as shown in 

Channel 0

Arbiter

Channel Priority Level

Channel Pending

Transfer Request

Priority

decoder

ACTIVE.LVLEXx

PRICTRLx.LVLPRI

Channel Burst Done

Burst Done

Channel Suspend

Active

Channel

Channel Number

Channel N

CTRL.LVLENx

Level Enable

Channel Enable

Channel Suspend

Channel Priority Level

Channel Burst Done

Channel Enable

Channel Pending