Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

The arbitration procedure is performed after each burst transfer. If the current DMA channel is granted access again, the 
block transfer counter (

) of the internal transfer descriptor will be decremented with the number of beats in a 

burst, and the active channel will perform a new burst transfer. If a different DMA channel than the current active channel 
is granted access, the 

 of the internal transfer descriptor will be decremented with the number of beats in a burst. 

The block transfer counter value will be written to the write-back section before the transfer descriptor of the newly 
granted DMA channel is fetched into the internal memory of the active channel. The optional output event, Beat, will be 
generated if configured and enabled.

When a block transfer has come to its end, 

 has reached zero, the Valid bit in the Block Transfer Control register 

will be written to zero in the internal transfer descriptor for the active channel before the entire transfer descriptor is 
written to the write-back memory. The optional interrupts, Channel Transfer Complete and Channel Suspend, and the 
optional output event, Block, will be generated if configured and enabled. If it was the last block transfer in a transaction, 
Next Address (

) register will hold the value 0x00000000, and the DMA channel will either be suspended or 

disabled, depending on the configuration in the Block Action bit group in the Block Transfer Control 
register(

.BLOCKACT). If the transaction has further block transfers pending, 

 will hold the SRAM 

address to the next transfer descriptor to be fetched. The DMAC will fetch the next descriptor into the internal memory of 
the active channel and write its content to the write-back section for the channel, before the arbiter gets to choose the 
next active channel.

A DMA transfer can be started only when a DMA transfer request is detected. A transfer request can be triggered from 
software, from peripheral, or from an event. There are dedicated Trigger Source selections for each DMA Channel 
Control B (

.TRIGSRC). 

The trigger actions are available in the Trigger Action bit group in the Channel Control B register (

.TRIGACT). 

By default, a trigger starts a block transfer operation. If a single descriptor is defined for a channel, the channel is 
automatically disabled when a block transfer is complete. If a list of linked descriptors is defined for a channel, the 
channel is automatically disabled if the last descriptor in the list is executed or the channel will be waiting for the next 
block transfer trigger if the list still has descriptors to execute. When enabled again, the channel will wait for the next 
block transfer trigger. It is also possible to select the trigger to start beat or transaction transfers instead of a block 
transfer.

If the trigger source generates a transfer request during an ongoing transfer, this will be kept pending 
(CHSTATUS.PEND is one), and the transfer can start when the ongoing one is done. Only one pending transfer can be 
kept, and so if the trigger source generates more transfer requests when one is already pending, these will be lost. All 
channels pending status flags are also available in the Pending Channels register (PENDCH).

When the transfer starts, the corresponding Channel Busy status flag is set in Channel Status register 
(CHSTATUS.BUSY). When the trigger action is complete, the Channel Busy status flag is cleared. All channels busy 
status flags are also available in the Busy Channels register (BUSYCH) in DMAC.

 shows an example where triggers are used with two linked block descriptors.