Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
29
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
10.3 Micro Trace Buffer
10.3.1 Features
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Program flow tracing for the Cortex-M0+ processor
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MTB SRAM can be used for both trace and general purpose storage by the processor
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The position and size of the trace buffer in SRAM is configurable by software
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CoreSight compliant
10.3.2 Overview
When enabled, the MTB records changes in program flow, reported by the Cortex-M0+ processor over the execution
trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+. This information is stored as
trace packets in the SRAM by the MTB. An off-chip debugger can extract the trace information using the Debug Access
Port to read the trace information from the SRAM. The debugger can then reconstruct the program flow from this
information.
trace interface shared between the Cortex-M0+ processor and the CoreSight MTB-M0+. This information is stored as
trace packets in the SRAM by the MTB. An off-chip debugger can extract the trace information using the Debug Access
Port to read the trace information from the SRAM. The debugger can then reconstruct the program flow from this
information.
The MTB simultaneously stores trace information into the SRAM, and gives the processor access to the SRAM. The
MTB ensures that trace write accesses have priority over processor accesses.
MTB ensures that trace write accesses have priority over processor accesses.
The execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects the processor PC
value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception
entry. See the CoreSight MTB-M0+ Technical Reference Manual for more details on the MTB execution trace packet
format.
value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception
entry. See the CoreSight MTB-M0+ Technical Reference Manual for more details on the MTB execution trace packet
format.
Tracing is enabled when the MASTER.EN bit in the Master Trace Control Register is 1. There are various ways to set the
bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical Reference Manual for more
details on the Trace start and stop and for a detailed description of the MTB’s MASTER register. The MTB can be
programmed to stop tracing automatically when the memory fills to a specified watermark level or to start or stop tracing
by writing directly to the MASTER.EN bit. If the watermark mechanism is not being used and the trace buffer overflows,
then the buffer wraps around overwriting previous trace packets.
bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical Reference Manual for more
details on the Trace start and stop and for a detailed description of the MTB’s MASTER register. The MTB can be
programmed to stop tracing automatically when the memory fills to a specified watermark level or to start or stop tracing
by writing directly to the MASTER.EN bit. If the watermark mechanism is not being used and the trace buffer overflows,
then the buffer wraps around overwriting previous trace packets.
The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM Table. The
offset of each register from the base address is fixed and as defined by the CoreSight MTB-M0+ Technical Reference
Manual. The MTB has 4 programmable registers to control the behavior of the trace features:
offset of each register from the base address is fixed and as defined by the CoreSight MTB-M0+ Technical Reference
Manual. The MTB has 4 programmable registers to control the behavior of the trace features:
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POSITION: Contains the trace write pointer and the wrap bit,
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MASTER: Contains the main trace enable bit and other trace control fields,
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FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits,
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BASE: Indicates where the SRAM is located in the processor memory map. This register is provided to enable
auto discovery of the MTB SRAM location, by a debug agent.
auto discovery of the MTB SRAM location, by a debug agent.
See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.
10.4 High-Speed Bus System
10.4.1 Features
High-Speed Bus Matrix has the following features:
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Symmetric crossbar bus switch implementation
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Allows concurrent accesses from different masters to different slaves
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32-bit data bus
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Operation at a one-to-one clock frequency with the bus masters