Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

To ensure that masters with latency requirements get sufficient priority when accesing RAM, the different masters can be 
configured to have a given priority for different type of access.

The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any access to the 
RAM the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level

.

If a master is configured with QoS level 0x00 or 0x01 there will be minimum one cycle latency for the RAM access.

The priority order for concurrent accesses are decided by two factors. First the QoS level for the master and then a static 
priority given by table nn-mm (table: SRAM port connection) where the lowest port ID has the highest static priority. 

The MTB has fixed QoS level 3 and the DSU has fixed QoS level 1.

The CPU QoS level can be written/read at address 0x41007110, bits [1:0]. Its reset value is 0x0.

Refer to different master QOSCTRL registers for configuring QoS for the other masters(USB, DMAC).

MTB - Micro Trace Buffer

0

Direct

USB - Universal Serial Bus

1

Direct

DMAC - Direct Memory Access Controller - Write-Back Access

2

Direct

DMAC - Direct Memory Access Controller - Fetch Access

3

Direct

CM0+ - Cortex M0+ Processor

4

Bus Matrix

DMAC - Direct Memory Access Controller - Data Access

5

Bus Matrix

DSU - Device Service Unit

6

Bus Matrix

00

DISABLE 

Background (no sensitive operation)

01

LOW

Sensitive Bandwidth

10

MEDIUM

Sensitive Latency

11

HIGH

Critical Latency