Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
475
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
26.6.4 DMA, Interrupts and Events
26.6.4.1 DMA Operation
The SPI generates the following DMA requests:
z
Data received (RX): The request is set when data is available in the receive FIFO. The request is cleared when
DATA is read.
DATA is read.
z
Data transmit (TX): The request is set when the transmit buffer (TX DATA) is empty. The request is cleared when
DATA is written.
DATA is written.
26.6.4.2 Interrupts
The SPI has the following interrupt sources:
z
Error (ERROR): this is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
z
Slave Select Low (SSL): his is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
mode.
z
Receive Complete (RXC): his is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
mode.
z
Transmit Complete (TXC): his is an asynchronous interrupt and can be used to wake-up the device from any sleep
mode.
mode.
z
Data Register Empty (DRE): his is an asynchronous interrupt and can be used to wake-up the device from any
sleep mode.
sleep mode.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the SPI is reset. See the register description for details on how to clear interrupt flags.
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the SPI is reset. See the register description for details on how to clear interrupt flags.
The SPI has one common interrupt request line for all the interrupt sources. The user must read INTFLAG to determine
which interrupt condition is present.
which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to
For details on clearing interrupt flags, refer to
26.6.4.3 Events
Not applicable.
Table 26-3. Module Request for SERCOM SPI
Condition
Interrupt request
Event output
Event input
DMA request
DMA request is
cleared
Data Register
Empty
Empty
x
x
When data is
written
Transmit
Complete
Complete
x
Receive
Complete
Complete
x
x
When data is read
Slave Select low
x
Error
x