Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
476
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
26.6.5 Sleep Mode Operation
During master operation, the generic clock will continue to run in idle sleep mode. If the Run In Standby bit in the Control
A register (CTRLA.RUNSTDBY) is one, the GCLK_SERCOM_CORE will also be enabled in standby sleep mode. Any
interrupt can wake up the device.
A register (CTRLA.RUNSTDBY) is one, the GCLK_SERCOM_CORE will also be enabled in standby sleep mode. Any
interrupt can wake up the device.
If CTRLA.RUNSTDBY is zero during master operation, GLK_SERCOMx_CORE will be disabled when the ongoing
transaction is finished. Any interrupt can wake up the device.
transaction is finished. Any interrupt can wake up the device.
During slave operation, writing a one to CTRLA.RUNSTDBY will allow the Receive Complete interrupt to wake up the
device.
device.
If CTRLA.RUNSTDBY is zero during slave operation, all reception will be dropped, including the ongoing transaction.
26.6.6 Synchronization
Due to the asynchronicity between CLK_SERCOMx_APB and GCLK_SERCOMx_CORE, some registers must be
synchronized when accessed. A register can require:
synchronized when accessed. A register can require:
z
Synchronization when written
z
Synchronization when read
z
Synchronization when written and read
z
No synchronization
When executing an operation that requires synchronization, the corresponding Synchronization Busy bit in the
Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete.
If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is one, a peripheral bus
error is generated.
error is generated.
The following bits need synchronization when written:
z
Software Reset bit in the Control A register (CTRLA.SWRST). SYNCBUSY.SWRST is set to one while
synchronization is in progress.
synchronization is in progress.
z
Enable bit in the Control A register (CTRLA.ENABLE). SYNCBUSY.ENABLE is set to one while synchronization is
in progress.
in progress.
z
Receiver Enable bit in the Control B register (CTRLB.RXEN). SYNCBUSY.CTRLB is set to one while
synchronization is in progress.
synchronization is in progress.
CTRLB.RXEN behaves somewhat differently than described above. Refer to CTRLB for details.
Write-synchronization is denoted by the Write-Synchronized property in the register description.