Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

In Transmitter mode, when DATAm is empty, Transmit Ready bit (TXRDYm) in the Interrupt Flag Status and Clear 
register (INTFLAG) is set. Writing to DATAm will clear this bit.

A transmit underrun condition occurs if a new data word needs to be transmitted before it has been written to DATAm. 
Then, Transmit Underrun (TXURm) bit in INTFLAG will be set. This interrupt can be cleared by writing a one to 
INTFLAG.TXURm bit. If TXSAME bit in SERCTRLm is zero, then a zero data word is transmitted in case of underrun. If 
SERCTRLm.TXSAME is one, then the previous data word for the current transmit slot number is transmitted.

In Master and Controller modes, the I

2

S provides the Serial Clock, Word Select/Frame Sync signal and optionally Master 

Clock.

In Controller mode, the I

2

S Serializers are disabled. Only the clocks are enabled and output to be used by external 

receivers and/or transmitters.

In Slave mode, the I

2

S receives the Serial Clock and the Word Select/Frame Sync Signal from an external master. SCKn 

and FSn pins are inputs.

As specified in the I

2

S protocol, data bits are left-adjusted in the Word Select slot, with the MSB transmitted first, starting 

one clock period after the transition on the Word Select line.

Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial Clock. The Word 
Select line indicates the channel in transmission, a low level for the left channel and a high level for the right channel.

In I

2

S format, typical configurations are described below. These configurations do not list all necessary settings, but only 

basic ones. Other configuration settings are to be done as per requirement such as clock and DMA configurations.

Case 1: I

2

S 16-bit compact stereo

Slot size configured as 16 bits (CLKCTRL0.SLOTSIZE = 0x1)

Number of slots configured as 2 (CLKCTRL0.NBSLOTS = 0x1)

Data size configured as 16-bit compact stereo (SERCTRL0.DATASIZE = 0x05)

Data delay from Frame Sync configured as 1-bit delay (CLKCTRLn.BITDELAY = 0x01) 

Frame Sync Width configured as HALF frame (CLKCTRLn.FSWIDTH = 0x01)

Case 2: I

2

S 24-bit stereo with 24-bit slot

Slot size configured as 24 bits (CLKCTRL0.SLOTSIZE = 0x2)

Number of slots configured as 2 (CLKCTRL0.NBSLOTS = 0x1)

Data size configured as 24 bits (SERCTRL0.DATASIZE = 0x01)

Data delay from Frame Sync configured as 1-bit delay (CLKCTRLn.BITDELAY = 0x01) 

Bit Serial Clock 

SCKn

Word Select   

FSn

Data               

SDm

MSB

Left Channel

LSB

MSB

Right Channel