Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
573
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
Frame Sync Width configured as HALF frame (CLKCTRLn.FSWIDTH = 0x01)
In both cases, it will ensure that Word select signal is 'low level' for the left channel and 'high level' for the right channel.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the Data Word Size bit
group in the Serializer Control m register (SERCTRLm.DATASIZE).
group in the Serializer Control m register (SERCTRLm.DATASIZE).
If the slot allows for more data bits than the number of bits specified in the SERCTRLm.DATASIZE field, additional bits
are appended to the transmitted or received data word as specified in SERCTRLm.EXTEND field. If the slot allows less
data bits than programmed, the extra bits are not transmitted, or received data word is extended based on the
SERCTRLm.EXTEND field.
are appended to the transmitted or received data word as specified in SERCTRLm.EXTEND field. If the slot allows less
data bits than programmed, the extra bits are not transmitted, or received data word is extended based on the
SERCTRLm.EXTEND field.
28.6.5 TDM Format - Reception and Transmission Sequence
In Time Division Multiplexed (TDM) format, the number of data slots sent or received within each frame will be
(CLKCTRLn.NBSLOTS + 1).
(CLKCTRLn.NBSLOTS + 1).
By configuring the CLKCTRLn register (CLKCTRLn.FSWIDTH and CLKCTRLn.FSINV), the Frame Sync pulse width and
polarity can be modified.
polarity can be modified.
By configuring SERCTRLm, data bits can be left-adjusted or right-adjusted in the slot. It can also configure the data
transmission/reception with either the MSB or the LSB transmitted/received first and starting the transmission/reception
either at the transition of the FSn pin or one clock period after.
transmission/reception with either the MSB or the LSB transmitted/received first and starting the transmission/reception
either at the transition of the FSn pin or one clock period after.
Figure 28-6. TDM Format Reception and Transmission Sequence
Data bits are sent on the falling edge of the Serial Clock and sampled on the rising edge of the Serial Clock. The FSn pin
provides a frame synchronization signal, at the beginning of slot 0. The delay between the frame start and the first data
bit is defined by writing the CLKCTRLn.BITDELAY field.
provides a frame synchronization signal, at the beginning of slot 0. The delay between the frame start and the first data
bit is defined by writing the CLKCTRLn.BITDELAY field.
The Frame Sync pulse can be either one SCKn period (BIT), one slot (SLOT), or one half frame (HALF). This selection is
done by writing the CLKCTRLn.FSWIDTH field.
done by writing the CLKCTRLn.FSWIDTH field.
The number of slots is selected by writing the CLKCTRLn.NBSLOTS field.
The number of bits in each slot is selected by writing the CLKCTRLn.SLOTSIZE field.
The length of transmitted words can be chosen among 8, 16, 18, 20, 24, and 32 bits by writing the DATASIZE field in the
Serializer Control register (SERCTRLm).
Serializer Control register (SERCTRLm).
If the slot allows more data bits than the number of bits specified in the SERCTRLm.DATASIZE field, additional bits are
appended to the transmitted or received data word as specified in SERCTRLm.EXTEND field. If the slot allows less data
bits than programmed, the extra bits are not transmitted, or received data word is extended based on the
SERCTRLm.EXTEND field.
appended to the transmitted or received data word as specified in SERCTRLm.EXTEND field. If the slot allows less data
bits than programmed, the extra bits are not transmitted, or received data word is extended based on the
SERCTRLm.EXTEND field.
28.6.6 PDM Reception
In Pulse Density Modulation (PDM) reception mode, continuous 1-bit data samples are available on the SDm line on
each SDm line on each SCKn rising edge, e.g. by a MEMS microphone with PDM interface. When using two channel
PDM microphones, the second one for right channel is configured to output data on each SCKn falling edge.
each SDm line on each SCKn rising edge, e.g. by a MEMS microphone with PDM interface. When using two channel
PDM microphones, the second one for right channel is configured to output data on each SCKn falling edge.
For one PDM microphone, the I
2
S controller should be configured in normal Receive mode with one slot and 16- or 32-bit
Datasize, so that 16 or 32 samples of the microphone are stored into each Data word.
Slot 0
Slot 2
Slot 1
Slot 3
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
Serial Clock (SCKn)
Frame Sync (FSn)
Data (SDm)
HALF
SLOT
BIT