Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

The DMAC transfers may use 32-bit word, 16-bit halfword, or 8-bit byte according to the value of the 
SERCTRLm.DATASIZE field. 8-bit compact stereo uses 16-bit halfwords and 16-bit compact stereo uses 32-bit words.

The I

2

S has the following interrupt sources:

z

Receive Ready (RXRDYm): this is an asynchronous interrupt and can be used to wake-up the device from any 
sleep mode.

z

Receive Overrun (RXORm): this is an asynchronous interrupt and can be used to wake-up the device from any 
sleep mode.

z

Transmit Ready (TXRDYm): this is an asynchronous interrupt and can be used to wake-up the device from any 
sleep mode.

z

Transmit Underrun (TXORm): this is an asynchronous interrupt and can be used to wake-up the device from any 
sleep mode.

Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear 
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one 
to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the 
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the interrupt 
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is 
cleared, the interrupt is disabled, or the I

2

S is reset. See 

 for details on how to clear interrupt flags. All interrupt 

requests from the peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. 
Refer to 

 for details. The user must read the INTFLAG register to 

determine which interrupt condition is present.

Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to 

Not applicable.

The I

2

S continues to operate in all sleep modes that still provide its clocks.

Due to the asynchronicity between CLK_I2S_APB and GCLK_I2S_n some registers must be synchronized when 
accessed. A register can require:

z

Synchronization when written

z

Synchronization when read

z

Synchronization when written and read

z

No synchronization

When executing an operation that requires synchronization, the corresponding Synchronization Busy bit in the 
Synchronization Busy register (SYNCBUSY) will be set immediately, and cleared when synchronization is complete.

If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is one, a peripheral bus 
error is generated.

The following bits require synchronization when written:

z

Software Reset bit in the Control A register (CTRLA.SWRST). SYNCBUSY.SWRST is set to one while 
synchronization is in progress.

z

Enable bit in the Control A register (CTRLA.ENABLE). SYNCBUSY.ENABLE is set to one while synchronization is 
in progress.

z

Clock Unit x Enable bits in the Control A register (CTRLA.CKENx). SYNCBUSY.CKENx is set to one while 
synchronization is in progress.