Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet

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Atmel | SMART SAM D21 [DATASHEET]

Atmel-42181C–SAM-D21_Datasheet–07/2014

After writing a one to CTRLA.ENABLE, the USB enters device or host mode (according to CTRLA.MODE). Please refer 

.

The USB can be disabled at any time by writing a zero to CTRLA.ENABLE.

 for the basic operation of the device mode.

 for the basic operation of the host mode.

This section gives an overview of the USB module device operation during normal transactions. For more details on 
general USB and USB protocol, please refer to the Universal Serial Bus specification revision 2.1.

To attach the USB device to start the USB communications from the USB host, a zero should be written to the Detach bit 
in the Device Control B register (CTRLB.DETACH). To detach the device from the USB host, a one must be written to the 
CTRLB.DETACH.

After the device is attached, the host will request the USB device descriptor using the default device address zero. On 
successful transmission, it will send a USB reset. After that, it sends an address to be configured for the device. All 
further transactions will be directed to this device address. This address should be configured in the Device Address field 
in the Device Address register (DADD.DADD) and the Address Enable bit in DADD (DADD.ADDEN) should be written to 
one to accept the communications directed to this address. DADD.ADDEN is automatically cleared on receiving a USB 
reset.

Endpoint data can be placed anywhere in the device RAM. The USB controller accesses these endpoints directly 
through the AHB master (built-in DMA) with the help of the endpoint descriptors. The base address of the endpoint 
descriptors needs to be written in the Descriptor Address register (DESCADD) by the user. Please refer the Endpoint 
Descriptor structure in 

Before using an endpoint, the user should configure the direction and type of the endpoint in Type of Endpoint field in the 
Device Endpoint Configuration register (EPCFG.EPTYPE0/1). The endpoint descriptor registers should be initialized to 
known values before using the endpoint, so that the USB controller does not read the random values from the RAM. 

The Endpoint Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported to the 
host for that endpoint. The Address of Data Buffer register (ADDR) should be set to the data buffer used for endpoint 
transfers.

The Ram Access Interrupt bit in Device Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM access 
underflow error occurs during IN data stage.

When an endpoint is disabled, the following registers are cleared for that endpoint:

z

Device Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register

z

Device Endpoint Interrupt Flag (EPINTFLAG) register

z

Transmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0)

z

Transmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1)

Multi-packet transfer enables a data payload exceeding the endpoint maximum transfer size to be transferred as multiple 
packets without software intervention. This reduces the number of interrupts and software intervention required to 
manage higher level USB transfers. Multi-packet transfer is identical to the IN and OUT transactions described below 
unless otherwise noted in this section.

The application software provides the size and address of the RAM buffer to be proceeded by the USB module for a 
specific endpoint, and the USB module will split the buffer in the required USB data transfers without any software 
intervention.