Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Data Sheet
Product codes
ATSAMD21-XPRO
739
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
PCKSIZE.SIZE, the remainders of the received data bytes are discarded. The packet will still be checked for bit-stuff and
CRC errors. Software must never report a endpoint size to the host that is greater than the value configured in
PCKSIZE.SIZE. If a bit-stuff or CRC error is detected in the packet, the USB module returns to idle and waits for the next
token packet.
CRC errors. Software must never report a endpoint size to the host that is greater than the value configured in
PCKSIZE.SIZE. If a bit-stuff or CRC error is detected in the packet, the USB module returns to idle and waits for the next
token packet.
If data is successfully received, an ACK handshake is returned to the host, and the number of received data bytes,
excluding the CRC, is written to the Byte Count (PCKSIZE.BYTE_COUNT). If the number of received data bytes is the
maximum data payload specified by PCKSIZE.SIZE, no CRC data is written to the data buffer. If the number of received
data bytes is the maximum data payload specified by PCKSIZE.SIZE minus one, only the first CRC data is written to the
data buffer. If the number of received data is equal or less than the data payload specified by PCKSIZE.SIZE minus two,
both CRC data bytes are written to the data buffer.
excluding the CRC, is written to the Byte Count (PCKSIZE.BYTE_COUNT). If the number of received data bytes is the
maximum data payload specified by PCKSIZE.SIZE, no CRC data is written to the data buffer. If the number of received
data bytes is the maximum data payload specified by PCKSIZE.SIZE minus one, only the first CRC data is written to the
data buffer. If the number of received data is equal or less than the data payload specified by PCKSIZE.SIZE minus two,
both CRC data bytes are written to the data buffer.
Finally the EPSTATUS is updated. Data Toggle OUT bit (EPSTATUS.DTGLOUT), the Data Toggle IN bit
(EPSTATUS.DTGLIN), the current bank bit (EPSTATUS.CURRBK) and the Bank Ready 0 bit (EPSTATUS.BK0RDY) are
set. Bank Ready 1 bit (EPSTATUS.BK1RDY) and the Stall Bank 0/1 bit (EPSTATUS.STALLQR0/1) are cleared on
receiving the SETUP request. The RXSTP bit is set and triggers an interrupt if the Received Setup Interrupt Enable bit is
set in Endpoint Interrupt Enable Set/Clear register (EPINTENSET/CLR.RXSTP).
(EPSTATUS.DTGLIN), the current bank bit (EPSTATUS.CURRBK) and the Bank Ready 0 bit (EPSTATUS.BK0RDY) are
set. Bank Ready 1 bit (EPSTATUS.BK1RDY) and the Stall Bank 0/1 bit (EPSTATUS.STALLQR0/1) are cleared on
receiving the SETUP request. The RXSTP bit is set and triggers an interrupt if the Received Setup Interrupt Enable bit is
set in Endpoint Interrupt Enable Set/Clear register (EPINTENSET/CLR.RXSTP).
31.6.2.7 Management of OUT Transactions
Figure 31-4. OUT Transfer: Data Packet Host to USB Device
When a OUT token is detected and the device address of the token packet does not match DADD.DADD, the packet is
discarded and the USB module returns to idle and waits for the next token packet.
discarded and the USB module returns to idle and waits for the next token packet.
If the address matches, the USB module checks if the endpoint number received is enabled in the EPCFG of the
addressed endpoint. If the addressed endpoint is disabled, the packet is discarded and the USB module returns to idle
and waits for the next token packet.
addressed endpoint. If the addressed endpoint is disabled, the packet is discarded and the USB module returns to idle
and waits for the next token packet.
When the endpoint is enabled, the USB module then checks the Endpoint Configuration register (EPCFG) of the
addressed output endpoint. If the type of the endpoint (EPCFG.EPTYPE0) is not set to OUT, the USB module returns to
idle and waits for the next token packet.
addressed output endpoint. If the type of the endpoint (EPCFG.EPTYPE0) is not set to OUT, the USB module returns to
idle and waits for the next token packet.
Internal RAM
USB Module
USB Endpoints
Descriptor Table
DESCADD
USB I/O Registers
USB Buffers
ENDPOINT 1 DATA
ENDPOINT 2 DATA
ENDPOINT 3 DATA
D
A
T
A
0
A
T
A
0
D
A
T
A
A
T
A
0
D
A
A
T
A
0
A
0
D
A
T
A
1
A
T
A
1
D
A
A
T
A
0
A
0
D
A
T
A
1
A
T
A
1
D
A
T
A
0
A
T
A
0
D
A
T
A
1
A
T
A
1
D
A
T
A
0
A
T
A
0
D
A
T
A
1
A
T
A
1
D
A
T
A
0
A
T
A
0
BULK OUT
EPT 2
BULK OUT
EPT 3
BULK OUT
EPT 1
DP
DM
HOST
time
Memory Map
I/O Register