Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
137
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
• Bit 4, 3 – Reserved
These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see
“Interrupts” on page 58) is executed when the OCF1B Flag, located in TIFR1, is set.
Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding Interrupt Vector (see
“Interrupts” on page 58) is executed when the OCF1B Flag, located in TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see
“Interrupts” on page 58) is executed when the OCF1A Flag, located in TIFR1, is set.
Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding Interrupt Vector (see
“Interrupts” on page 58) is executed when the OCF1A Flag, located in TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the
Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See
Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector (See
)
is executed when the TOV1 Flag, located in TIFR1, is set.
16.11.9 TIFR1 – Timer/Counter1 Interrupt Flag Register
• Bit 7, 6 – Reserved
These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by
the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value.
the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be
cleared by writing a logic one to its bit location.
cleared by writing a logic one to its bit location.
• Bit 4, 3 – Reserved
These bits are unused bits in the ATmega48A/PA/88A/PA/168A/PA/328/P, and will always read as zero.
• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register B
(OCR1B).
(OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively,
OCF1B can be cleared by writing a logic one to its bit location.
OCF1B can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output Compare Register A
(OCR1A).
(OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
Bit
7
6
5
4
3
2
1
0
–
–
ICF1
–
–
OCF1B
OCF1A
TOV1
TIFR1
Read/Write
R
R
R/W
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0