Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
152
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
Figure 18-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f
clk_I/O
/8)
18.9
Asynchronous Operation of Timer/Counter2
When Timer/Counter2 operates asynchronously, some considerations must be taken.
Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer
Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source
is:
Registers TCNT2, OCR2x, and TCCR2x might be corrupted. A safe procedure for switching clock source
is:
a. Disable the Timer/Counter2 interrupts by clearing OCIE2x and TOIE2.
2. Select clock source by setting AS2 as appropriate.
3. Write new values to TCNT2, OCR2x, and TCCR2x.
4. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB.
5. Clear the Timer/Counter2 Interrupt Flags.
6. Enable interrupts, if needed.
3. Write new values to TCNT2, OCR2x, and TCCR2x.
4. To switch to asynchronous operation: Wait for TCN2xUB, OCR2xUB, and TCR2xUB.
5. Clear the Timer/Counter2 Interrupt Flags.
6. Enable interrupts, if needed.
The CPU main clock frequency must be more than four times the Oscillator frequency.
When writing to one of the registers TCNT2, OCR2x, or TCCR2x, the value is transferred to a temporary
register, and latched after two positive edges on TOSC1. The user should not write a new value before the
contents of the temporary register have been transferred to its destination. Each of the five mentioned
registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb
an OCR2x write in progress. To detect that a transfer to the destination register has taken place, the
Asynchronous Status Register – ASSR has been implemented.
register, and latched after two positive edges on TOSC1. The user should not write a new value before the
contents of the temporary register have been transferred to its destination. Each of the five mentioned
registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb
an OCR2x write in progress. To detect that a transfer to the destination register has taken place, the
Asynchronous Status Register – ASSR has been implemented.
When entering Power-save or ADC Noise Reduction mode after having written to TCNT2, OCR2x, or
TCCR2x, the user must wait until the written register has been updated if Timer/Counter2 is used to wake
up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is
particularly important if any of the Output Compare2 interrupt is used to wake up the device, since the
Output Compare function is disabled during writing to OCR2x or TCNT2. If the write cycle is not finished,
and the MCU enters sleep mode before the corresponding OCR2xUB bit returns to zero, the device will
never receive a compare match interrupt, and the MCU will not wake up.
TCCR2x, the user must wait until the written register has been updated if Timer/Counter2 is used to wake
up the device. Otherwise, the MCU will enter sleep mode before the changes are effective. This is
particularly important if any of the Output Compare2 interrupt is used to wake up the device, since the
Output Compare function is disabled during writing to OCR2x or TCNT2. If the write cycle is not finished,
and the MCU enters sleep mode before the corresponding OCR2xUB bit returns to zero, the device will
never receive a compare match interrupt, and the MCU will not wake up.
If Timer/Counter2 is used to wake the device up from Power-save or ADC Noise Reduction mode,
precautions must be taken if the user wants to re-enter one of these modes: If re-entering sleep mode
within the TOSC1 cycle, the interrupt will immediately occur and the device wake up again. The result is
multiple interrupts and wake-ups within one TOSC1 cycle from the first interrupt. If the user is in doubt
whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following
algorithm can be used to ensure that one TOSC1 cycle has elapsed:
precautions must be taken if the user wants to re-enter one of these modes: If re-entering sleep mode
within the TOSC1 cycle, the interrupt will immediately occur and the device wake up again. The result is
multiple interrupts and wake-ups within one TOSC1 cycle from the first interrupt. If the user is in doubt
whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following
algorithm can be used to ensure that one TOSC1 cycle has elapsed:
a. Write a value to TCCR2x, TCNT2, or OCR2x.
7. Wait until the corresponding Update Busy Flag in ASSR returns to zero.
8. Enter Power-save or ADC Noise Reduction mode.
8. Enter Power-save or ADC Noise Reduction mode.
When the asynchronous operation is selected, the 32.768kHz Oscillator for Timer/Counter2 is always
running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-
down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one
running, except in Power-down and Standby modes. After a Power-up Reset or wake-up from Power-
down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1
TOP
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)