Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
153
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after
power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers
must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal
upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.
power-up or wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers
must be considered lost after a wake-up from Power-down or Standby mode due to unstable clock signal
upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.
Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked
asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle
of the timer clock, that is, the timer is always advanced by at least one before the processor can read the
counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and
resumes execution from the instruction following SLEEP.
asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle
of the timer clock, that is, the timer is always advanced by at least one before the processor can read the
counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and
resumes execution from the instruction following SLEEP.
Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result.
Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a
register synchronized to the internal I/O clock domain. Synchronization takes place for every rising
TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clk
Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a
register synchronized to the internal I/O clock domain. Synchronization takes place for every rising
TOSC1 edge. When waking up from Power-save mode, and the I/O clock (clk
I/O
) again becomes active,
TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The
phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it
depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows:
phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it
depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows:
a. Write any value to either of the registers OCR2x or TCCR2x.
9. Wait for the corresponding Update Busy Flag to be cleared.
10. Read TCNT2.
10. Read TCNT2.
During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes
3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor
can read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the
timer clock and is not synchronized to the processor clock.
3 processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor
can read the timer value causing the setting of the Interrupt Flag. The Output Compare pin is changed on the
timer clock and is not synchronized to the processor clock.
18.10 Timer/Counter Prescaler
Figure 18-12. Prescaler for Timer/Counter2
The clock source for Timer/Counter2 is named clk
T2S
. clk
T2S
is by default connected to the main system I/O
clock clk
IO
. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin.
This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2
10-BIT T/C PRESCALER
TIMER/COUNTER2 CLOCK SOURCE
clk
I/O
clk
T2S
TOSC1
AS2
CS20
CS21
CS22
clk
T2S
/8
clk
T2S
/64
clk
T2S
/128
clk
T2S
/1024
clk
T2S
/256
clk
T2S
/32
0
PSRASY
Clear
clk
T2