Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet

168

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271H-AVR- ATmega-Datasheet_08/2014

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the Global 
Interrupt Enable bit in SREG is set.

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is 
configured as an input and is driven low while MSTR is set, MSTR will be cleared, and SPIF in SPSR will 
become set. The user will then have to set MSTR to re-enable SPI Master mode.

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. 
Refer to 

 and 

 for an example. The CPOL functionality is summarized below:

The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) 
edge of SCK. Refer to 

 and 

 for an example. The CPOL functionality is summarized 

below:

These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on 
the Slave. The relationship between SCK and the Oscillator Clock frequency f

osc 

is shown in the following table: 

Bit

7

6

5

4

3

2

1

0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

CPOL Functionality

0

Rising

Falling

1

Falling

Rising

CPHA Functionality

0

Sample

Setup

1

Setup

Sample