Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
183
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
contain any unread data). If the Receiver is disabled (RXENn = 0), the receive buffer will be flushed and
consequently the RXCn bit will become zero.
consequently the RXCn bit will become zero.
When the Receive Complete Interrupt Enable (RXCIEn) in UCSRnB is set, the USART Receive Complete
interrupt will be executed as long as the RXCn Flag is set (provided that global interrupts are enabled). When
interrupt-driven data reception is used, the receive complete routine must read the received data from UDRn in
order to clear the RXCn Flag, otherwise a new interrupt will occur once the interrupt routine terminates.
interrupt will be executed as long as the RXCn Flag is set (provided that global interrupts are enabled). When
interrupt-driven data reception is used, the receive complete routine must read the received data from UDRn in
order to clear the RXCn Flag, otherwise a new interrupt will occur once the interrupt routine terminates.
20.7.4 Receiver Error Flags
The USART Receiver has three Error Flags: Frame Error (FEn), Data OverRun (DORn) and Parity Error
(UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the
receive buffer together with the frame for which they indicate the error status. Due to the buffering of the Error
Flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location
changes the buffer read location. Another equality for the Error Flags is that they can not be altered by software
doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward
compatibility of future USART implementations. None of the Error Flags can generate interrupts.
(UPEn). All can be accessed by reading UCSRnA. Common for the Error Flags is that they are located in the
receive buffer together with the frame for which they indicate the error status. Due to the buffering of the Error
Flags, the UCSRnA must be read before the receive buffer (UDRn), since reading the UDRn I/O location
changes the buffer read location. Another equality for the Error Flags is that they can not be altered by software
doing a write to the flag location. However, all flags must be set to zero when the UCSRnA is written for upward
compatibility of future USART implementations. None of the Error Flags can generate interrupts.
The Frame Error (FEn) Flag indicates the state of the first stop bit of the next readable frame stored in the
receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one), and the FEn Flag will be one
when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting
break conditions and protocol handling. The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC
since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this
bit to zero when writing to UCSRnA.
receive buffer. The FEn Flag is zero when the stop bit was correctly read (as one), and the FEn Flag will be one
when the stop bit was incorrect (zero). This flag can be used for detecting out-of-sync conditions, detecting
break conditions and protocol handling. The FEn Flag is not affected by the setting of the USBSn bit in UCSRnC
since the Receiver ignores all, except for the first, stop bits. For compatibility with future devices, always set this
bit to zero when writing to UCSRnA.
The Data OverRun (DORn) Flag indicates data loss due to a receiver buffer full condition. A Data OverRun
occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register,
and a new start bit is detected. If the DORn Flag is set there was one or more serial frame lost between the
frame last read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always
write this bit to zero when writing to UCSRnA. The DORn Flag is cleared when the frame received was
successfully moved from the Shift Register to the receive buffer.
occurs when the receive buffer is full (two characters), it is a new character waiting in the Receive Shift Register,
and a new start bit is detected. If the DORn Flag is set there was one or more serial frame lost between the
frame last read from UDRn, and the next frame read from UDRn. For compatibility with future devices, always
write this bit to zero when writing to UCSRnA. The DORn Flag is cleared when the frame received was
successfully moved from the Shift Register to the receive buffer.
The Parity Error (UPEn) Flag indicates that the next frame in the receive buffer had a Parity Error when
received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future
devices, always set this bit to zero when writing to UCSRnA. For more details see
received. If Parity Check is not enabled the UPEn bit will always be read zero. For compatibility with future
devices, always set this bit to zero when writing to UCSRnA. For more details see
and
20.7.5 Parity Checker
The Parity Checker is active when the high USART Parity mode (UPMn1) bit is set. Type of Parity Check to be
performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity
of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of
the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn)
Flag can then be read by software to check if the frame had a Parity Error.
performed (odd or even) is selected by the UPMn0 bit. When enabled, the Parity Checker calculates the parity
of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of
the check is stored in the receive buffer together with the received data and stop bits. The Parity Error (UPEn)
Flag can then be read by software to check if the frame had a Parity Error.
The UPEn bit is set if the next character that can be read from the receive buffer had a Parity Error when
received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer
(UDRn) is read.
received and the Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer
(UDRn) is read.
20.7.6 Disabling the Receiver
In contrast to the Transmitter, disabling of the Receiver will be immediate. Data from ongoing receptions will
therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will no longer override the normal
function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled.
Remaining data in the buffer will be lost
therefore be lost. When disabled (i.e., the RXENn is set to zero) the Receiver will no longer override the normal
function of the RxDn port pin. The Receiver buffer FIFO will be flushed when the Receiver is disabled.
Remaining data in the buffer will be lost