Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
184
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
20.7.7 Flushing the Receive Buffer
The receiver buffer FIFO will be flushed when the Receiver is disabled, i.e., the buffer will be emptied of its
contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an
error condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows
how to flush the receive buffer.
contents. Unread data will be lost. If the buffer has to be flushed during normal operation, due to for instance an
error condition, read the UDRn I/O location until the RXCn Flag is cleared. The following code example shows
how to flush the receive buffer.
Note:
1.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must
be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with
“SBRS”, “SBRC”, “SBR”, and “CBR”.
be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with
“SBRS”, “SBRC”, “SBR”, and “CBR”.
20.8
Asynchronous Data Reception
The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The
clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming
asynchronous serial frames at the RxDn pin. The data recovery logic samples and low pass filters each
incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational
range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame
size in number of bits.
clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming
asynchronous serial frames at the RxDn pin. The data recovery logic samples and low pass filters each
incoming bit, thereby improving the noise immunity of the Receiver. The asynchronous reception operational
range depends on the accuracy of the internal baud rate clock, the rate of the incoming frames, and the frame
size in number of bits.
20.8.1 Asynchronous Clock Recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames.
illustrates the
sampling process of the start bit of an incoming frame. The sample rate is 16 times the baud rate for Normal
mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the
synchronization variation due to the sampling process. Note the larger time variation when using the Double
Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (i.e.,
no communication activity).
mode, and eight times the baud rate for Double Speed mode. The horizontal arrows illustrate the
synchronization variation due to the sampling process. Note the larger time variation when using the Double
Speed mode (U2Xn = 1) of operation. Samples denoted zero are samples done when the RxDn line is idle (i.e.,
no communication activity).
Figure 20-5.
Start Bit Sampling
Assembly Code Example
USART_Flush:
in r16, UCSRnA
sbrs r16, RXCn
ret
in
r16, UDRn
rjmp
USART_Flush
C Code Example
void USART_Flush( void )
{
unsigned char dummy;
while ( UCSRnA & (1<<RXCn) ) dummy = UDRn;
}
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
START
IDLE
0
0
BIT 0
3
1
2
3
4
5
6
7
8
1
2
0
RxD
Sample
(U2X = 0)
Sample
(U2X = 1)