Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet

Product codes
MEGA328P-XMINI
Page of 657
198
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
BAUD
Baud rate (in bits per second, bps)
f
OSC
System Oscillator clock frequency
UBRRn
Contents of the UBRRnH and UBRRnL Registers, (0-4095)
21.4
SPI Data Modes and Timing
There are four combinations of XCKn (SCK) phase and polarity with respect to serial data, which are 
determined by control bits UCPHAn and UCPOLn. The data transfer timing diagrams are shown in 
Data bits are shifted out and latched in on opposite edges of the XCKn signal, ensuring sufficient time for data 
signals to stabilize. The UCPOLn and UCPHAn functionality is summarized in 
the setting of any of these bits will corrupt all ongoing communication for both the Receiver and Transmitter.
Figure 21-1.
UCPHAn and UCPOLn data transfer timing diagrams.
21.5
Frame Formats
A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two 
valid frame formats:
8-bit data with MSB first
8-bit data with LSB first
A frame starts with the least or most significant data bit. Then the next data bits, up to a total of eight, are 
succeeding, ending with the most or least significant bit accordingly. When a complete frame is transmitted, a 
new frame can directly follow it, or the communication line can be set to an idle (high) state.
The UDORDn bit in UCSRnC sets the frame format used by the USART in MSPIM mode. The Receiver and 
Transmitter use the same setting. Note that changing the setting of any of these bits will corrupt all ongoing 
communication for both the Receiver and Transmitter.
16-bit data transfer can be achieved by writing two data bytes to UDRn. A UART transmit complete interrupt will 
then signal that the 16-bit value has been shifted out.
Table 21-2.
UCPOLn and UCPHAn Functionality-
UCPOLn
UCPHAn
SPI Mode
Leading Edge
Trailing Edge
0
0
0
Sample (Rising)
Setup (Falling)
0
1
1
Setup (Rising)
Sample (Falling)
1
0
2
Sample (Falling)
Setup (Rising)
1
1
3
Setup (Falling)
Sample (Rising)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
UCPOL=0
UCPOL=1
UCPHA=0
UCPHA=1