Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI Data Sheet
Product codes
MEGA328P-XMINI
40
ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]
Atmel-8271H-AVR- ATmega-Datasheet_08/2014
10.
Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR
provides various sleep modes allowing the user to tailor the power consumption to the application’s
requirements.
provides various sleep modes allowing the user to tailor the power consumption to the application’s
requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during the sleep
periods. To further save power, it is possible to disable the BOD in some sleep modes. See
periods. To further save power, it is possible to disable the BOD in some sleep modes. See
10.1
Sleep Modes
presents the different clock systems in the ATmega48A/PA/88A/PA/168A/PA/328/P, and
their distribution. The figure is helpful in selecting an appropriate sleep mode.
shows the different
sleep modes, their wake up sources BOD disable ability.
Note:
1. BOD disable is only available for ATmega48PA/88PA/168PA/328P.
Notes: 1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT1 and INT0, only level interrupt.
3. For INT1 and INT0, only level interrupt.
To enter any of the six sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction
must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC
Noise Reduction, Power-down, Power-save, Standby, or Extended Standby) will be activated by the SLEEP
instruction. See
must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC
Noise Reduction, Power-down, Power-save, Standby, or Extended Standby) will be activated by the SLEEP
instruction. See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for
four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the
instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes
up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the
instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes
up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.
Table 10-1.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Oscillators
Wake-up Sources
Sof
tware
BOD Disab
le
Sleep Mode
clk
CPU
clk
FL
AS
H
clk
IO
clk
ADC
clk
ASY
Mai
n Clock
So
urce Enabl
ed
T
ime
r Oscilla
to
r
En
able
d
INT
1, INT
0
and
Pi
n C
han
ge
T
W
I Address
Match
Ti
m
e
r2
SPM/EE
P
ROM
R
eady
ADC
WDT
Other I/O
Idle
X
X
X
X
X
X
X
X
X
X
X
X
ADC Noise
Reduction
Reduction
X
X
X
X
X
X
X
Power-down
X
X
X
Power-save
X
X
X
X
X
Standby
X
X
X
X
Extended
Standby
Standby
X
X
X
X
X
X