Intel 1.40 GHz RH80532NC017256 Data Sheet

92 Datasheet

 

298517-006 

other conditions in are met, the processor restarts its internal clock to all units and resumes execution. 
The assertion of STPCLK# has no affect on the bus clock. 

The TCK (Test Clock) signal provides the clock input for the test bus (also known as the test access 
port).  

The TDI (Test Data In) signal transfers serial test data to the processor. TDI provides the serial input 
needed for JTAG support. 

The TDO (Test Data Out) signal transfers serial test data from the processor. TDO provides the serial 
output needed for JTAG support. 

The TESTHI[2:1] (Test input High) signals are used during processor test and need to be pulled high 
during normal operation.  

The TESTLO[2:1] (Test input Low) signals are used during processor test and needs to be pulled to 
ground during normal operation.  

The THERMDA (Thermal Diode Anode) and THERMDC (Thermal Diode Cathode) signals connect to 
the anode and cathode of the on-die thermal diode. 

The TMS (Test Mode Select) signal is a JTAG support signal used by debug tools. 

The TRDY# (Target Ready) signal is asserted by the target to indicate that the target is ready to receive 
write or implicit write-back data transfer. TRDY# must be connected to the appropriate pins/balls on 
both agents on the system bus. 

The TRST# (Test Reset) signal resets the Test Access Port (TAP) logic. The Mobile Intel Celeron 
Processors do not self-reset during power on; therefore, it is necessary to drive this signal low during 
power-on reset.