Intel 1.40 GHz RH80532NC017256 Data Sheet
Product codes
RH80532NC017256
Mobile Intel
®
Celeron
®
Processor (0.13 µ)
Micro-FCBGA and Micro-FCPGA Packages Datasheet
298517-006 Datasheet
93
VID[4:0] (O – Open-drain)
The VID[4:0] (Voltage ID) pins/balls can be used to support automatic selection of power supply
voltages. Please refer to Section 3.2.3 for details.
voltages. Please refer to Section 3.2.3 for details.
VREF (Analog)
The VREF (AGTL Reference Voltage) signal provides a DC level reference voltage for the AGTL input
buffers. A voltage divider should be used to divide V
buffers. A voltage divider should be used to divide V
CCT
by
2
/
3
. Resistor values of 1.00 k
Ω and 2.00 kΩ
are recommended. Decouple the VREF signal with three 0.1-
µF high-frequency capacitors close to the
processor.
VTTPWRGD (I – 1.25 V)
The VTTPWRGD signal informs the processor to output the VID signals. During power up, the VID
signals will be in an indeterminate state for a small period of time. The voltage regulator should not
sample and/or latch the VID signals until the VTTPWRGD signal is asserted. The assertion of the
VTTPWRGD signal indicates that the VID signals are stable and are driven to the final state by the
processor. Please refer to Figure 15 for the power up sequence. (Also see Section 4.3.1.)
signals will be in an indeterminate state for a small period of time. The voltage regulator should not
sample and/or latch the VID signals until the VTTPWRGD signal is asserted. The assertion of the
VTTPWRGD signal indicates that the VID signals are stable and are driven to the final state by the
processor. Please refer to Figure 15 for the power up sequence. (Also see Section 4.3.1.)