Intel E3-1105C AV8062701048800 Data Sheet

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

-

001

153

B/D/F/Type:

0/0/0/PCI

Address Offset:

CA-CBh

Default Value:

0000h

Access:

RO; RW

Size:

16 bits

BIOS Optimal Default

0000h

This register controls the Host Bridge responses to various system errors. Since the 

Host Bridge does not have an SERRB signal, SERR messages are passed from the 

Processor to the PCH over DMI.

When a bit in this register is set, a SERR message will be generated on DMI whenever 

the corresponding flag is set in the ERRSTS register. The actual generation of the SERR 

message is globally enabled for Device 0 via the PCI Command register.

1

RW1C-S

0b

Powergood

Multiple-bit DRAM ECC Error Flag (DMERR): If this bit 

is set to 1, a memory read data transfer had an 

uncorrectable multiple-bit error. When this bit is set, 

the column, row, bank, and rank that caused the error, 

and the error syndrome, are logged in the ECC Error 

Log register in the channel where the error occurred. 

Once this bit is set, the ECCERRLOGx fields are locked 

until the processor clears this bit by writing a 1. 

Software uses bits [1:0] to detect whether the logged 

error address is for a Single-bit or a Multiple-bit error. 

This bit is reset on PWROK.

0

RW1C-S

0b

Powergood

Single-bit DRAM ECC Error Flag (DSERR): If this bit is 

set to 1, a memory read data transfer had a single-bit 

correctable error and the corrected data was returned 

to the requesting agent. When this bit is set the 

column, row, bank, and rank where the error occurred 

and the syndrome of the error are logged in the ECC 

Error Log register in the channel where the error 

occurred. Once this bit is set the ECCERRLOGx fields 

are locked to further single-bit error updates until the 

CPU clears this bit by writing a 1. A multiple bit error 

that occurs after this bit is set will overwrite the 

ECCERRLOGx fields with the multiple-bit error 

signature and the DMERR bit will also be set. A single 

bit error that occurs after a multibit error will set this 

bit but will not overwrite the other fields. This bit is 

reset on PWROK.