Intel E3-1105C User Manuals

Table of Contents

• Intel® Xeon® and Intel® Core™ Processors For Communications Infrastructure

  1
  • Legal Lines and Disclaimers

    2
  • Revision History

    3
  • Contents

    4
    • Figures

      6
    • Tables

      7
• 1.0 Introduction

  11
  • 1.1 Purpose / Scope / Audience

    11
  • 1.2 Related Documents

    11
  • 1.3 Terminology

    13
• 2.0 Product Overview

  15
  • 2.1 Product Features

    17
  • 2.2 Processor Details

    17
  • 2.3 Supported Technologies

    17
  • 2.4 Interface Features

    17
    • 2.4.1 System Memory Support

      17
    • 2.4.2 PCI Express*

      18
    • 2.4.3 Direct Media Interface (DMI)

      20
    • 2.4.4 Platform Environment Control Interface (PECI)

      20
  • 2.5 Power Management Support

    21
    • 2.5.1 Processor Core

      21
    • 2.5.2 System

      21
    • 2.5.3 Memory Controller

      21
    • 2.5.4 PCI Express*

      21
    • 2.5.5 DMI

      21
  • 2.6 Thermal Management Support

    21
  • 2.7 Package

    21
  • 2.8 Testability

    21
• 3.0 Interfaces

  23
  • 3.1 System Memory Interface

    23
    • 3.1.1 System Memory Configurations Supported

      23
      • 3.1.1.1 UDIMM Configurations

        24
      • 3.1.1.2 SO-DIMM Configurations

        25
      • 3.1.1.3 Memory Down Configurations

        26
    • 3.1.2 System Memory Timing Support

      26
    • 3.1.3 System Memory Organization Modes

      27
      • 3.1.3.1 Single-Channel Mode

        27
      • 3.1.3.2 Dual-Channel Mode - Intel® Flex Memory Technology Mode

        27
    • 3.1.4 Rules for Populating Memory Slots

      28
    • 3.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

      28
      • 3.1.5.1 Just-in-Time Command Scheduling

        29
      • 3.1.5.2 Command Overlap

        29
      • 3.1.5.3 Out-of-Order Scheduling

        29
      • 3.1.5.4 Memory Type Range Registers (MTRRs) Enhancement

        29
    • 3.1.6 Data Scrambling

      29
    • 3.1.7 DRAM Clock Generation

      29
  • 3.2 PCI Express* Interface

    29
    • 3.2.1 PCI Express* Architecture

      30
      • 3.2.1.1 Transaction Layer

        31
      • 3.2.1.2 Data Link Layer

        31
      • 3.2.1.3 Physical Layer

        31
    • 3.2.2 PCI Express* Configuration Mechanism

      32
    • 3.2.3 PCI Express* Port Bifurcation

      32
    • 3.2.4 PCI Express* Lanes Connection

      34
    • 3.2.5 Configuring PCIe* Lanes

      35
    • 3.2.6 Lane Reversal on PCIe* Interface

      36
  • 3.3 Direct Media Interface

    36
    • 3.3.1 DMI Error Flow

      36
    • 3.3.2 DMI Link Down

      36
  • 3.4 Platform Environment Control Interface (PECI)

    36
  • 3.5 Interface Clocking

    37
    • 3.5.1 Internal Clocking Requirements

      37
• 4.0 Technologies

  39
  • 4.1 Intel® Virtualization Technology

    39
    • 4.1.1 Intel® VT-x Objectives

      39
    • 4.1.2 Intel® VT-x Features

      39
    • 4.1.3 Intel® VT-d Objectives

      40
    • 4.1.4 Intel® VT-d Features

      40
    • 4.1.5 Intel® VT-d Features Not Supported

      41
  • 4.2 Intel® Hyper-Threading Technology

    41
  • 4.3 Intel® Advanced Vector Extensions (Intel® AVX)

    41
  • 4.4 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

    42
    • 4.4.1 PCLMULQDQ Instruction

      42
  • 4.5 Intel® 64 Architecture x2APIC

    42
• 5.0 Processor SKUs

  45
  • 5.1 Overview

    45
    • 5.1.1 SKU Features

      45
• 6.0 Power Management

  47
  • 6.1 ACPI States Supported

    48
    • 6.1.1 System States

      48
    • 6.1.2 Processor Core/Package Idle States

      48
    • 6.1.3 Integrated Memory Controller States

      48
    • 6.1.4 PCIe* Link States

      49
    • 6.1.5 DMI States

      49
    • 6.1.6 Interface State Combinations

      49
  • 6.2 Processor Core Power Management

    49
    • 6.2.1 Enhanced Intel SpeedStep® Technology

      50
    • 6.2.2 Low-Power Idle States

      50
    • 6.2.3 Requesting Low-Power Idle States

      51
    • 6.2.4 Core C-states

      52
      • 6.2.4.1 Core C0 State

        52
      • 6.2.4.2 Core C1/C1E State

        52
      • 6.2.4.3 Core C3 State

        53
      • 6.2.4.4 Core C6 State

        53
      • 6.2.4.5 Core C7 State

        53
      • 6.2.4.6 C-State Auto-Demotion

        53
    • 6.2.5 Package C-States

      53
      • 6.2.5.1 Package C0

        55
      • 6.2.5.2 Package C1/C1E

        55
      • 6.2.5.3 Package C3 State

        56
      • 6.2.5.4 Package C6 State

        56
      • 6.2.5.5 Package C7 State

        56
      • 6.2.5.6 Dynamic L3 Cache Sizing

        56
  • 6.3 IMC Power Management

    57
    • 6.3.1 Disabling Unused System Memory Outputs

      57
    • 6.3.2 DRAM Power Management and Initialization

      57
      • 6.3.2.1 Initialization Role of CKE

        59
      • 6.3.2.2 Dynamic Power Down Operation

        59
      • 6.3.2.3 DRAM I/O Power Management

        59
  • 6.4 PCIe* Power Management

    59
  • 6.5 DMI Power Management

    59
  • 6.6 Thermal Power Management

    59
• 7.0 Thermal Management

  61
  • 7.1 Thermal Design Power (TDP) and Junction Temperature (TJ)

    61
  • 7.2 Thermal and Power Specifications

    61
  • 7.3 Thermal Management Features

    63
    • 7.3.1 Processor Package Thermal Features

      63
      • 7.3.1.1 Adaptive Thermal Monitor

        63
      • 7.3.1.2 Digital Thermal Sensor

        65
      • 7.3.1.3 PROCHOT# Signal

        66
    • 7.3.2 Processor Core Specific Thermal Features

      68
      • 7.3.2.1 On-Demand Mode

        68
    • 7.3.3 Memory Controller Specific Thermal Features

      68
      • 7.3.3.1 Programmable Trip Points

        68
    • 7.3.4 Platform Environment Control Interface (PECI)

      68
      • 7.3.4.1 Fan Speed Control with Digital Thermal Sensor

        69
• 8.0 Signal Description

  71
  • 8.1 System Memory Interface

    71
  • 8.2 Memory Reference and Compensation

    74
  • 8.3 Reset and Miscellaneous Signals

    74
  • 8.4 PCI Express* Based Interface Signals

    75
  • 8.5 DMI

    75
  • 8.6 PLL Signals

    76
  • 8.7 TAP Signals

    76
  • 8.8 Error and Thermal Protection

    77
  • 8.9 Power Sequencing

    78
  • 8.10 Processor Power and Ground Signals

    78
  • 8.11 Sense Pins

    79
  • 8.12 Future Compatibility

    79
  • 8.13 Processor Internal Pull Up/Pull Down

    79
• 9.0 Electrical Specifications

  81
  • 9.1 Power and Ground Pins

    81
  • 9.2 Decoupling Guidelines

    81
    • 9.2.1 Voltage Rail Decoupling

      81
  • 9.3 Processor Clocking (BCLK, BCLK#)

    82
    • 9.3.1 PLL Power Supply

      82
  • 9.4 Serial Voltage Identification (SVID)

    82
  • 9.5 System Agent (SA) Vcc VID

    89
  • 9.6 Reserved or Unused Signals

    90
  • 9.7 Signal Groups

    90
  • 9.8 Test Access Port (TAP) Connection

    92
  • 9.9 Storage Conditions Specifications

    92
  • 9.10 DC Specifications

    93
    • 9.10.1 Voltage and Current Specifications

      94
    • 9.10.2 Platform Environmental Control Interface DC Specifications

      99
      • 9.10.2.1 PECI Bus Architecture

        99
      • 9.10.2.2 PECI DC Characteristics

        100
      • 9.10.2.3 Input Device Hysteresis

        101
  • 9.11 AC Specifications

    101
    • 9.11.1 DDR3 AC Specifications

      103
    • 9.11.2 PCI Express* AC Specification

      107
    • 9.11.3 Miscellaneous AC Specifications

      108
    • 9.11.4 TAP Signal Group AC Specifications

      108
    • 9.11.5 SVID Signal Group AC Specifications

      109
  • 9.12 Processor AC Timing Waveforms

    109
  • 9.13 Signal Quality

    114
    • 9.13.1 Input Reference Clock Signal Quality Specifications

      115
    • 9.13.2 DDR3 Signal Quality Specifications

      115
    • 9.13.3 I/O Signal Quality Specifications

      115
  • 9.14 Overshoot/Undershoot Guidelines

    115
    • 9.14.1 VCC Overshoot Specification

      115
    • 9.14.2 Overshoot/Undershoot Magnitude

      116
    • 9.14.3 Overshoot/Undershoot Pulse Duration

      116
• 10.0 Processor Ball and Package Information

  119
  • 10.1 Processor Ball Assignments

    119
  • 10.2 Package Mechanical Information

    146
• 11.0 Processor Configuration Registers

  151
  • 11.1 ERRSTS - Error Status

    152
  • 11.2 ERRCMD - Error Command

    153
  • 11.3 SMICMD - SMI Command

    154
  • 11.4 SCICMD - SCI Command

    155
  • 11.5 ECCERRLOG0_C0 - ECC Error Log 0

    155
  • 11.6 ECCERRLOG1_C0 - ECC Error Log 1

    156
  • 11.7 ECCERRLOG0_C1 - ECC Error Log 0

    157
  • 11.8 ECCERRLOG1_C1 - ECC Error Log 1

    158
  • 11.9 MAD_DIMM_CH0 - Address Decode Channel 0

    158
  • 11.10 MAD_DIMM_CH1 - Address Decode Channel 1

    160
  • 11.11 Error Detection and Correction

    161