Intel E3-1105C AV8062701048800 Data Sheet

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

42

Document Number: 327405

-

001

The processor supports Advanced Encryption Standard New Instructions (Intel

®

 AES-

NI), which are a set of Single Instruction Multiple Data (SIMD) instructions that enable 

fast and secure data encryption and decryption based on the Advanced Encryption 

Standard (AES). Intel

®

 AES-NI are valuable for a wide range of cryptographic 

applications, for example: applications that perform bulk encryption/decryption, 

authentication, random number generation, and authenticated encryption. AES is 

broadly accepted as the standard for both government and industry applications, and is 

widely deployed in various protocols.

Intel

®

 AES-NI consists of six Intel

®

 SSE instructions. Four instructions, namely 

AESENC, AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES 

encryption and decryption. The other two, namely AESIMC and AESKEYGENASSIST, 

support the AES key expansion procedure. Together, these instructions provide a full 

hardware for support AES, offering security, high performance, and a great deal of 

flexibility.

The processor supports the carry-less multiplication instruction, PCLMULQDQ. 

PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the 

128-bit carry-less multiplication of two, 64-bit operands without generating and 

propagating carries. Carry-less multiplication is an essential processing component of 

several cryptographic systems and standards. Hence, accelerating carry-less 

multiplication can significantly contribute to achieving high speed secure computing 

and communication.

The x2APIC architecture extends the xAPIC architecture which provides key mechanism 

for interrupt delivery. This extension is intended primarily to increase processor 

addressability. 

Specifically, x2APIC:

• Retains all key elements of compatibility to the xAPIC architecture:

— delivery modes
— interrupt and processor priorities
— interrupt sources
— interrupt destination types

• Provides extensions to scale processor addressability for both the logical and 

physical destination modes.

• Adds new features to enhance performance of interrupt delivery.
• Reduces complexity of logical destination mode interrupt delivery on link based 

architectures.

The key enhancements provided by the x2APIC architecture over xAPIC are the 

following:

• Support for two modes of operation to provide backward compatibility and 

extensibility for future platform innovations.

— In xAPIC compatibility mode, APIC registers are accessed through memory 

mapped interface to a 4K-Byte page, identical to the xAPIC architecture.