Intel E3-1105C AV8062701048800 Data Sheet
Product codes
AV8062701048800
Electrical Specifications
Intel
®
Xeon
®
and Intel
®
Core™ Processors For Communications Infrastructure
Datasheet - Volume 1 of 2
May 2012
82
Document Number: 327405
-
001
9.3
Processor Clocking (BCLK, BCLK#)
The processor utilizes a differential clock to generate the processor core(s) operating
frequency, memory controller frequency, and other internal clocks. The processor core
frequency is determined by multiplying the processor core ratio by 100 MHz. Clock
multiplying within the processor is provided by an internal phase locked loop (PLL),
which requires a constant frequency input, with exceptions for Spread Spectrum
Clocking (SSC).
The processor’s maximum core frequency is configured during power-on reset by using
its manufacturing default value. This value is the highest core multiplier at which the
processor can operate. If lower maximum speeds are desired, the appropriate ratio can
be configured via the FLEX_RATIO MSR.
9.3.1
PLL Power Supply
An on-die PLL filter solution is implemented on the processor.
9.4
Serial Voltage Identification (SVID)
The SVID specifications for the processor V
CC
is defined in the VR12 / IMVP7 SVID
Protocol. The processor
uses three signals for the serial voltage identification interface
to support automatic selection of voltages.
specifies the voltage level
corresponding to the eight bit VID value transmitted over serial VID. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. If the voltage
regulation circuit cannot supply the voltage that is requested, the voltage regulator
must disable itself. VID signals are CMOS push/pull drivers. The VID codes change due
to temperature and/or current load changes in order to minimize the power of the part.
A voltage range is provided in
. The specifications are set so that one voltage
regulator can operate with all supported frequencies.
Individual processor VID values may be set during manufacturing so that two devices
at the same core frequency may have different default VID settings. This is shown in
the VID range values in
. The processor
provides the ability to operate while
transitioning to an adjacent VID and its associated voltage. This represents a DC shift
in the loadline.
Note:
Transitions above the maximum specified VID are not permitted.
includes VID
step sizes and DC shift ranges. Minimum and maximum voltages must be maintained.
The VR utilized must be capable of regulating its output to the value defined by the new
VID values issued. DC specifications for dynamic VID transitions are included in
while AC specifications are included in
.
Table 9-1.
IMVP7 Voltage Identification Definition (Sheet 1 of 8)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
V
CC_MAX
0
0
0
0
0
0
0
0
0
0
0.00000
0
0
0
0
0
0
0
1
0
1
0.25000
0
0
0
0
0
0
1
0
0
2
0.25500
0
0
0
0
0
0
1
1
0
3
0.26000
0
0
0
0
0
1
0
0
0
4
0.26500
0
0
0
0
0
1
0
1
0
5
0.27000
0
0
0
0
0
1
1
0
0
6
0.27500
0
0
0
0
0
1
1
1
0
7
0.28000