Intel E5-1428L CM8062001144000 Data Sheet

NID

Node ID (NID) or NodeID (NID). The processor implements up to 4-

bits of NodeID (NID).

NodeID

Node ID (NID) or NodeID (NID).

pcode

Pcode is microcode which is run on the dedicated microcontroller

within the PCU.

PCH

Platform Controller Hub. A chipset with centralized platform

capabilities including the main I/O interfaces along with display

connectivity, audio features, power management, manageability,

security and storage features.

PCU

Power Control Unit.

PCI Express 3.0

The third generation PCI Express specification that operates at

twice the speed of PCI Express 2.0 (8 Gb/s); PCI Express 3.0 is

completely backward compatible with PCI Express 1.0 and 2.0.

PCI Express 2.0

PCI Express Generation 2.0

PECI

Platform Environment Control Interface

Phit

An Intel

®

 QPI terminology defining bits at physical layer.

Processor

Includes the 64-bit cores, uncore, I/Os and package

Processor Core

The term "processor core" refers to Si die itself which can contain

multiple execution cores. Each execution core has an instruction

cache, data cache, and 256-KB L2 cache. All execution cores share

the L3 cache.

R3QPI

Intel QPI Agent. An internal logic block providing interface between

internal Ring and external Intel QPI.

Rank

A unit of DRAM corresponding four to eight devices in parallel,

ignoring ECC. These devices are usually, but not always, mounted

on a single side of a DDR4 DIMM.

RDIMM

Registered Dual In-line Memory Module

RTID

Request Transaction IDs are credits issued by the Cbo to track

outstanding transaction, and the RTIDs allocated to a Cbo are

topology dependent.

SCI

System Control Interrupt. Used in ACPI protocol.

SKU

Stock Keeping Unit (SKU) is a subset of a processor type with

specific features, electrical, power and thermal specifications. Not

all features are supported on all SKUs. A SKU is based on specific

use condition assumption.

SSE

Intel

®

 Streaming SIMD Extensions (Intel

®

 SSE)

SMBus

System Management Bus. A two-wire interface through which

simple system and power management related devices can

communicate with the rest of the system.

Storage Conditions

A non-operational state. The processor may be installed in a

platform, in a tray, or loose. Processors may be sealed in packaging

or exposed to free air. Under these conditions, processor landings

should not be connected to any supply voltages, have any I/Os

biased or receive any clocks. Upon exposure to "free air" (that is,

unsealed packaging or a device removed from packaging material)

the processor must be handled in accordance with moisture

sensitivity labeling (MSL) as indicated on the packaging material.

TAC

Thermal Averaging Constant

TDP

Thermal Design Power

Intel

®

 Xeon

®

 Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical

Datasheet

September 2014

12

Order No.: 330783-001