Intel E5-1428L CM8062001144000 Data Sheet

TSOD

Temperature Sensor On DIMM

UDIMM

Unbuffered Dual In-line Memory Module

Uncore

The portion of the processor comprising the shared LLC cache, Cbo,

IMC, HA, PCU, Ubox, IIO and Intel QPI link interface.

Unit Interval

Signaling convention that is binary and unidirectional. In this binary

signaling, one bit is sent for every edge of the forwarded clock,

whether it be a rising edge or a falling edge. If a number of edges

are collected at instances t 

1

 , t 

2

 , t 

n

 ,...., t 

k

 then the UI at

instance "n" is defined as: UI 

n

 = t 

n

 - t 

n-1

V

CCIN

Primary voltage input to the voltage regulators integrated into the

processor.

VSS

Processor ground

V

CCIO_IN

IO voltage supply input

V

CCD

DDR power rail

x1

Refers to a Link or Port with one Physical Lane

x4

Refers to a Link or Port with four Physical Lanes

x8

Refers to a Link or Port with eight Physical Lanes

x16

Refers to a Link or Port with sixteen Physical Lanes

The data contained within this document is final. It is the most accurate information

available by the publication date of this document. Electrical DC specifications are

based on estimated I/O buffer behavior.

Intel

®

 Xeon

®

 Processor E5-1600 and E5-2600 v3 Product Families, Volume 1 of 2, Electrical

September 2014

Datasheet

Order No.: 330783-001

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