Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1019
14.11.360 PCSRC—Offset 73000h
Performance Counter Source Register
Access Method
Default: 00000000h
15:8
00001000b
RW
GREEN_Y:
gamma correction mapping Green to Y
7:0
00001000b
RW
BLUE_U_CB:
gamma correction mapping blue to CB
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PERFOR
M
A
NC
E
_
C
O
U
N
TE
R_ENABL
E
RES
E
RVE
D
R
E
S
E
T_
C
O
U
N
TE
R
MAX_OR_MIN
SOURC
E
_FOR_PERFORM
ANC
E
_C
OU
NT
ER
RES
E
RV
ED_1
PERFO
R
MANCE_COUN
T
E
R_THRES
H
OL
D_V
A
LUE
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
PERFORMANCE_COUNTER_ENABLE:
This bit enables the performance counter.
0 = Performance counter is disabled
1 = Performance counter is enabled.
30
0b
RW
RESERVED:
Reserved.
29
0b
RW
RESET_COUNTER:
This bit indicates when the counter will be reset.
1 = Reset after each frame, summing all events in the frame
0 = Reset after each event within the frame
28
0b
RW
MAX_OR_MIN:
This bit tells whether the stored counter value for an event is the
maximum or the minimum value. The previous value is used to do the compare.
0 = Stored value is the maximum latency
1 = Stored value is the minimum latency