Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
5308
Datasheet
42.3.16
ELCR2—Offset 4D1h
Slave Edge/Level Control
Access Method
Default: 00h
7
4
0
0
0
0
0
0
0
0
0
ELC
RE
SE
RVED
Bit
Range
Default &
Access
Description
7:3
X
RW
ELC:
Edge Level Control (ECL[7:3]): In edge mode, (bit cleared), the interrupt is
recognized by a low to high transition. In level mode (bit set), the interrupt is
recognized by a high level.
2:0
0b
RO
RESERVED:
Reserved.
Type:
I/O Register
(Size: 8 bits)
7
4
0
0
0
0
0
0
0
0
0
ELC1
RESE
RVED
ELC2
RESE
RVE
D
1
Bit
Range
Default &
Access
Description
7:6
X
RW
ELC1:
Edge Level Control (ECL[15:14]): In edge mode, (bit cleared), the interrupt is
recognized by a low to high transition. In level mode (bit set), the interrupt is
recognized by a high level. Bit 7 applies to IRQ15, and bit 6 to IRQ14.
5
0b
RO
RESERVED:
Reserved.
4:1
X
RW
ELC2:
Edge Level Control (ECL[12:9]: In edge mode, (bit cleared), the interrupt is
recognized by a low to high transition. In level mode (bit set), the interrupt is
recognized by a high level. Bit 4 applies to IRQ12, bit 3 to IRQ11, bit 2 to IRQ10, and bit
1 to IRQ9.
0
0b
RO
RESERVED (RESERVED1):
Reserved.