Intel E3815 FH8065301567411 Data Sheet

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

1047

The CCI interface consists of an I

2

C bus which has a clock line and a bidirectional data 

line.

The MIPI-CSI-2 devices operate in a layered fashion. There are 5 layers identified at 
the receiver and transmitter ends.

MIPI-CSI-2 Functional Layers:

•

PHY Layer:

— An embedded electrical layer sends and detects start of packet signalling and 

end of packet signalling on the data lanes. It contains a serializer and 
deserializer unit to interface with the PPI / lane management unit. There is also 
a clock divider unit to source and receive the clock during different modes of 
operation.

•

PPI/Lane Management Unit:

— This layer does the lane buffering and distributes the data in the lanes as 

programmed in a round robin manner and also merges them for the PLI/Low 
Level Protocol unit.

•

PLI/Low Level Protocol Unit:

— This layer packetizes as well as de-packetizes the data with respect to channels, 

frames, colors and line formats. There are ECC generator and corrector units to 
recover the data free from errors in the packet headers. There is also a CRC 
checker or CRC generator unit to pack the payload data with CRC checksum bits 
for payload data protection.

•

Pixel/Byte to Byte/Pixel Packing Formats:

— Conversion of pixel formats to data bytes in the payload data is done depending 

on the type of image data supported by the application. It also re-converts the 
raw data bytes to pixel format understandable to the application layer.

•

Application:

— Depending on the type of formats, camera types, capability of the camera used 

by the transmitter, the application layer recovers the image formats and 
reproduces the image in the display unit. It also works on de-framing the data 
into pixel-to-packing formats. High level encoding and decoding of image data is 
handled in the application unit.

CSI Features:

• Compliant to CSI-2 MIPI specification for Camera Serial Interface (Version 1.00)
• Supports standard D-PHY transceiver compliant to the MIPI Specification
• Supports PHY data programmability up to four lanes.
• Supports PHY data time-out programming.
• Has controls to start and re-start the CSI-2 data transmission for synchronization 

failures and to support recovery.