Intel E3815 FH8065301567411 Data Sheet

Intel

Product codes

FH8065301567411

Intel

®

Atom™ Processor E3800 Product Family

Datasheet

1079

658h

4

“reg_gpd_gptimer_count_type_timer_4_type

(gpd_gptimer_count_type_timer_4)—Offset 658h” on page 1165

00000000h

65Ch

4

“reg_gpd_gptimer_count_type_timer_5_type

(gpd_gptimer_count_type_timer_5)—Offset 65Ch” on page 1165

00000000h

660h

4

“reg_gpd_gptimer_count_type_timer_6_type

(gpd_gptimer_count_type_timer_6)—Offset 660h” on page 1166

00000000h

664h

4

“reg_gpd_gptimer_count_type_timer_7_type

(gpd_gptimer_count_type_timer_7)—Offset 664h” on page 1167

00000000h

668h

4

“reg_gpd_gptimer_signal_select_timer_0_type

(gpd_gptimer_signal_select_timer_0)—Offset 668h” on page 1167

00000000h

66Ch

4

“reg_gpd_gptimer_signal_select_timer_1_type

(gpd_gptimer_signal_select_timer_1)—Offset 66Ch” on page 1168

00000000h

670h

4

“reg_gpd_gptimer_signal_select_timer_2_type

(gpd_gptimer_signal_select_timer_2)—Offset 670h” on page 1169

00000000h

674h

4

“reg_gpd_gptimer_signal_select_timer_3_type

(gpd_gptimer_signal_select_timer_3)—Offset 674h” on page 1169

00000000h

678h

4

“reg_gpd_gptimer_signal_select_timer_4_type

(gpd_gptimer_signal_select_timer_4)—Offset 678h” on page 1170

00000000h

67Ch

4

“reg_gpd_gptimer_signal_select_timer_5_type

(gpd_gptimer_signal_select_timer_5)—Offset 67Ch” on page 1171

00000000h

680h

4

“reg_gpd_gptimer_signal_select_timer_6_type

(gpd_gptimer_signal_select_timer_6)—Offset 680h” on page 1171

00000000h

684h

4

“reg_gpd_gptimer_signal_select_timer_7_type

(gpd_gptimer_signal_select_timer_7)—Offset 684h” on page 1172

00000000h

688h

4

“reg_gpd_gptimer_irq_trigger_value_0_type

(gpd_gptimer_irq_trigger_value_0)—Offset 688h” on page 1173

00000000h

68Ch

4

“reg_gpd_gptimer_irq_trigger_value_1_type

(gpd_gptimer_irq_trigger_value_1)—Offset 68Ch” on page 1173

00000000h

690h

4

“reg_gpd_gptimer_irq_timer_select_0_type

(gpd_gptimer_irq_timer_select_0)—Offset 690h” on page 1174

00000000h

694h

4

“reg_gpd_gptimer_irq_timer_select_1_type

(gpd_gptimer_irq_timer_select_1)—Offset 694h” on page 1174

00000000h

698h

4

“reg_gpd_gptimer_irq_enable_0_type (gpd_gptimer_irq_enable_0)—

Offset 698h” on page 1175

00000000h

69Ch

4

“reg_gpd_gptimer_irq_enable_1_type (gpd_gptimer_irq_enable_1)—

Offset 69Ch” on page 1175

00000000h

10000h

4

“reg_scp_stat_and_ctrl_type (scp_stat_and_ctrl)—Offset 10000h” on

000000A0h

10004h

4

“reg_scp_base_address_type (scp_base_address)—Offset 10004h” on

00000000h

10008h

4

“reg_scp_unused_2_type (scp_unused_2)—Offset 10008h” on page 1178

00000000h

10010h

4

“reg_scp_base_addr_seg_0_MI_xmem_master_int_type

(scp_base_addr_seg_0_MI_xmem_master_int)—Offset 10010h” on

00000000h

10014h

4

“reg_scp_base_addr_seg_0_MI_config_ilm_conf_ilm_master_type

(scp_base_addr_seg_0_MI_config_ilm_conf_ilm_master)—Offset 10014h”

00000000h

10018h

4

“reg_scp_unused_6_type (scp_unused_6)—Offset 10018h” on page 1180

00000000h

1001Ch

4

“reg_scp_unused_7_type (scp_unused_7)—Offset 1001Ch” on page 1180

00000000h

Table 178.

Summary of Image Signal Processor Memory Mapped I/O Registers—

ISPMMADR (Continued)

Offset

Size

Register ID—Description

Default Value