Intel E3815 FH8065301567411 Data Sheet

Product codes

FH8065301567411

Intel

Atom™ Processor E3800 Product Family

Datasheet

Figure 81

Test Reset (TAP_TRST#), Async GTL Input and PROCHOT# Timing Waveform ...

203

Figure 82

Clock Cycle Time .................................................................................. 204

Figure 83

Clock Timing ........................................................................................ 204

Figure 84

Valid Delay from Rising Clock Edge ......................................................... 204

Figure 85

Setup and Hold Times ........................................................................... 204

Figure 86

Float Delay .......................................................................................... 205

Figure 87

Pulse Width.......................................................................................... 205

Figure 88

Output Enable Delay ............................................................................. 205

Figure 89

Differential Clock Waveform (Measured Single-ended) ............................... 206

Figure 90

Differential Clock Waveform (Using Differential Probe for Measurement)....... 206

Figure 91

Package Mechanical Drawing .................................................................. 208

Figure 92

Soc Transaction Router Register Map....................................................... 317

Figure 93

HDMI Overview .................................................................................... 411

Figure 94

DisplayPort* Overview........................................................................... 412

Figure 95

3D Graphics Block Diagram .................................................................... 414

Figure 96

Camera Connectivity ........................................................................... 1039

Figure 97

Image Processing Components ............................................................. 1042

Figure 98

MIPI-CSI Bus Block Diagram ................................................................ 1046

Figure 99

MIPI CSI Register Map......................................................................... 1049

Figure 100

SD Memory Card Bus Topology............................................................. 1747

Figure 101

SDIO Device Bus Topology................................................................... 1748

Figure 102

eMMC Interface .................................................................................. 1748

Figure 103

Storage Control Cluster Register Map .................................................... 1750

Figure 104

SATA Register Map ............................................................................. 1923

Figure 105

xHCI and EHCI Port Mapping ................................................................ 2114

Figure 106

USB Host Controller Register Map ......................................................... 2118

Figure 107

Intel

HD Audio Register Map .............................................................. 2665

Figure 108

Audio Cluster Block Diagram ................................................................ 2801

Figure 109

Memory Connections for LPE ............................................................... 2802

Figure 110

SSP CCLK Structure ............................................................................ 2806

Figure 111

Programmable Serial Protocol Format .................................................... 2812

Figure 112

Programmable Serial Protocol Format (Consecutive Transfers) .................. 2812

Figure 113

Low Power Engine for Audio Register Map .............................................. 2818

Figure 114

PCIe* 2.0 Lane 0 Signal Example.......................................................... 3180

Figure 115

Root Port Configuration Options ............................................................ 3181

Figure 116

PCI Express Register Map .................................................................... 3184

Figure 117

SPI Interface Signals........................................................................... 3788

Figure 118

Clock Phase and Polarity ...................................................................... 3790

Figure 119

SIO - SPI Register Map........................................................................ 3792

Figure 120

Data Transfer on the I

C Bus................................................................ 3821

Figure 121

START and STOP Conditions ................................................................. 3822

Figure 122

Seven-Bit Address Format.................................................................... 3823

Figure 123

Ten-Bit Address Format ....................................................................... 3823

Figure 124

Master Transmitter Protocol ................................................................. 3824

Figure 125

Master Receiver Protocol...................................................................... 3825

Figure 126

START Byte Transfer ........................................................................... 3826

Figure 127

SIO - I

C Register Map ........................................................................ 3829

Figure 128

UART Data Transfer Flow ..................................................................... 4173

Figure 129

SIO - HSUART Register Map ................................................................. 4177

Figure 130

PWM Signals ...................................................................................... 4262

Figure 131

PWM Block Diagram ............................................................................ 4263

Figure 132

SIO - PWM Register Map...................................................................... 4265