Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

134

Datasheet

1.

V

IH

 is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value

2.

V

IL

 is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical low value.

3.

Measured at PMC_V1P8_G3/2.

1.

V

IL

 is defined as the maximum voltage level at the receiving agent that will be received as a logical low value. DRAM_VREF 

is normally DRAM_VDD_S4/2

2.

V

IH

 is defined as the minimum voltage level at the receiving agent that will be received as a logical high value. 

DRAM_VREF is normally DRAM_VDD_S4/2

3.

V

IH

 and V

OH

 may experience excursions above DRAM_VDD_S4. However, input signal drivers must comply with the signal 

quality specifications.

4.

RON is DRAM driver resistance whereas RTT_TERM is DRAM ODT resistance which is controlled by DRAM.

5.

DDR3L-1333 CLK buffer Ron is 26ohm and SR target is 4V/ns; DQ-DQS buffer Ron is 30ohms and SR target is 4V/ns; 

CMD/CTL buffer Ron is 20ohms and SR target is 1.8V/ns.

V

REF

I/O Voltage

PMC_V1P8_G3

V

IH

Input High Voltage

0.64*V

REF

V

REF

V

1

V

IL

Input Low Voltage

0

0.4*V

REF

V

2

Z

pd

Pull down Impedance

30

Ω

3

R

wpu

Weak Pull Impedance

1

4

kΩ

3

V

IL

Input Low 
Voltage

DRAM_VREF 

- 200mV

V

1

V

IH

Input High 
Voltage

DRAM_VREF 

+ 200mV

V

2,  3

V

OL

Output Low 
Voltage

(DRAM_VDD_S4 / 2)* (RON /

(RON+RVTT_TERM))

3,4

V

OH

Output High 
Voltage

DRAM_VDD_S4 - 

((DRAM_VDD_S4 /2)* 

(RON/(RON+RVTT_TERM))

V

3,4

I

IL

Input Leakage 
Current

5

µA

For  all 

DRAM 

Signals

R

ON

DDR3L-RS 
Clock Buffer 
strength

26

40

Ω

5

C

IO

DQ/DQS/DQS# 
DDR3L-RS IO 
Pin Capacitance

3.0

pF