Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
1768
Datasheet
Default: 0000h
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:17, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
rs
vd
b
oot_e
n
sp
i_
m
o
de
cmd
_
co
mp_ata
blk_s
el
data_tr
_
d
ir
au
to_cmd_en
blk_co
unt_e
n
dm
a_
en
Bit
Range
Default &
Access
Field Name (ID): Description
15:9
00h
RO
Reserved (rsvd):
Reserved.
8
0b
RW
BOOT_EN (boot_en):
To start boot operation for MMC4.3 1 - To start boot mode 0 -
Stop the boot read
7
0b
RW
SPI_MODE (spi_mode):
SPI mode enable bit. 1 - SPI mode 0 - SD mode
6
0b
RW
CMD_COMP_ATA (cmd_comp_ata):
Command Completion Signal Enable for CE-ATA
Device. ???1??? - Device will send command completion Signal ???0??? - Device will not
send command completion Signal
5
0b
RW
BLK_SEL (blk_sel):
Multi / Single Block Select This bit is set when issuing multiple-
block transfer commands using DAT line. For any other commands, this bit shall be set
to 0. If this bit is 0, it is not necessary to set the Block Count register. (Refer to Table 2-
8) 1 Multiple Block 0 Single Block
4
0b
RW
Data Transfer Direction Select (data_tr_dir):
This bit defines the direction of DAT
line data transfers. The bit is set to 1 by the Host Driver to transfer data from the SD
card to the SD Host Controller, and it is set to 0 for all other commands.
•
•
1 = Read (Card to Host)
•
0 = Write (Host to Card)
3:2
0b
RW
AUTO_CMD_EN (auto_cmd_en):
This field determines use of auto command
functions 00b - Auto Command Disabled 01b - Auto CMD12 Enable 10b - Auto CMD23
Enable 11b - Reserved
1
0b
RW
Block Count Enable (blk_count_en):
This bit is used to enable the Block Count
register, which is only relevant for multiple block transfers. When this bit is 0, the Block
Count register is disabled, which is useful in executing an infinite transfer. (Refer to
Table 2-8). If ADMA2 data transfer is more than 65535 blocks, this bit shall be set to 0.
In this case, data transfer length is designated by Descriptor Table.
•
•
1 = Enable
•
0 = Disable
0
0b
RW
DMA Enable (dma_en):
This bit enables DMA functionality as described in section 1.4.
DMA can be enabled only if it is supported as indicated in the Capabilities register. One
of the DMA modes can be selected by DMA Select in the Host Control register. If DMA is
not supported, this bit is meaningless and shall always read 0. If this bit is set to 1, a
DMA operation shall begin when the Host Driver writes to the upper byte of Command
register (00Fh).
•
•
1 = DMA Data transfer
•
0 = No data transfer or Non DMA data transfer