Intel E3815 FH8065301567411 Data Sheet

Intel

®

 Atom™ Processor E3800 Product Family

178

Datasheet

1.

Measured at A plug.

2.

Measured at A receptacle.

3.

Measured at B receptacle.

4.

Measured at A or B connector.

5.

Measured with RL of 1.425 kΩ

 to 3.6 V.

6.

Measured with RL of 14.25 kΩ

 to GND.

7.

Timing difference between the differential data signals.

8.

Measured at crossover point of differential data signals.

9.

The maximum load specification is the maximum effective capacitive load allowed that meets the target 

VBUS drop of 330 mV.

10.

Excluding the first transition from the Idle state.

11.

The two transitions should be a (nominal) bit time apart.

12.

For both transitions of differential signaling.

13.

Must accept as valid EOP.

14.

Single-ended capacitance of D+ or D- is the capacitance of D+/D- to all other conductors and, if 

present, shield in the cable. That is, to measure the single-ended capacitance of D+, short D-, VBUS, 

GND, and the shield line together and measure the capacitance of D+ to the other conductors.

15.

For high power devices (non-hubs) when enabled for remote wakeup.

CLOCK TIMINGS:

TLDRATH

S

Low-speed Data Rate for hubs and 
devices which are high-speed capable

1.499

25

1.500

75

Mb/s

TLDRATE

Low-speed Data Rate for hubs and 
devices which are not high-speed 
capable

1.477

5

1.522

5

MB/s

FULL-SPEED DATA TIMINGS

TUDJ1
TUDJ2

Upstream facing port source Jitter 
Total (including frequency 
tolerance): To Next Transition For 
Paired Transitions

-95

-150

95

150

ns
ns

7,8

46

TDDJ1
TDDJ2

Downstream facing port source 
Jitter Total (including frequency 
tolerance): To Next Transition For 
Paired Transitions

-25
-14

25
14

ns
ns

7,8

46

TLDEOP

Source Jitter for Differential
Transition to SE0 Transition

-40

100

ns

8,11

47

TLEOPT

Source SE0 interval of EOP

1.25

1.50

us

47