Intel E3815 FH8065301567411 Data Sheet
Product codes
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1821
16.8.2
Block Size Register (BLK_SIZE)—Offset 4h
This register is used to configure the number of bytes in a data block.
Access Method
Default: 0000h
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
00000000h
RW
SDMA System Address (sys_adr): (1) SDMA System Address
This register contains the system memory address for a SDMA transfer. When the Host
Controller stops a SDMA transfer, this register shall point to the system address of the
next contiguous data position. It can be accessed only if no transaction is executing
(i.e., after a transaction has stopped). Read operations during transfers may return an
invalid value.
The Host Driver shall initialize this register before starting a SDMA transaction. After
SDMA has stopped, the next system address of the next contiguous data position can be
read from this register.
The SDMA transfer waits at each boundary specified by the Host SDMA Buffer Boundary
in the Block Size register. The Host Controller generates a DMA Interrupt to request the
Host Driver to update this register. The Host Driver sets the next system address of the
next data position to this register.
When the uppermost byte of this register (003h) is written, the Host Controller restarts
the SDMA transfer.
When restarting SDMA by the Resume command or by setting Continue Request in the
Block Gap Control register, the Host Controller shall start at the next contiguous address
stored here in the SDMA System Address register. ADMA does not use this register. (2)
Argument 2
This register is used with the Auto CMD23 to set a 32-bit block count value to the
argument of the CMD23 while executing Auto CMD23.
If Auto CMD23 is used with ADMA, the full 32-bit block count value can be used. If Auto
CMD23 is used without AMDA, the available block count value is limited by the Block
Count register. 65535 blocks is the maximum value in this case.
Type:
Memory Mapped I/O Register
(Size: 16 bits)
Offset:
BAR Type:
PCI Configuration Register (Size: 32 bits)
BAR Reference:
[B:0, D:18, F:0] + 10h
15
12
8
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
tx_blk
_
size_12
bou
n
dar
y
tr
_blk_s
ize
Bit
Range
Default &
Access
Field Name (ID): Description
15
0b
RW
TX_BLK_SIZE_12 (tx_blk_size_12):
Transfer Block Size 12th bit. This bit is added to
support 4Kb Data block transfer.